A few weeks ago I gave a talk to a group of graduate students at Chalmers University of Technology in Gothenburg Sweden. The talk was part of a 12 week course (Chalmers Computing Labs Tech Talks) intended to bridge the world of academia and industry by inviting speakers to talk about difficult product problems (and solutions) from different industries. Professor Mary Sheeran, who invited me, wanted to hear more about the design process used to design the Epiphany parallel processor and the Parallella $99 single board computer.
Preparing the slides and doing a post-mortem on 7 years of parallel processor design was a fun (but exhausting…) trip down memory lane and the interaction with the (~30) students was fantastic!
The writing is terse but some of the (painful) lessons learned may be useful to folks working in the field of computer architecture and hardware development.
If anything is unclear or you want to discuss content just leave a comment…
Cheers,
Andreas
Hi Andy,
Very Cool job!
Please keep on.
Being Pioneer is never easy.
Awesome experience sharing!
Thanks!! Not giving up yet:-)
Tell us about the pic used? What are the tech specs? why did you build it?
pic?
The key specs/documents can be found here:
http://adapteva.com/docs
http://parallella.org/docs
Thanks for sharing the slides Andreas, I sent them round the lab mailing list for more to see – it’s a great insight into your journey. How do you feel about the decision not to have an on-chip memory PHY and controller has worked out? I noticed http://arxiv.org/abs/1410.8772 finds maximum off-chip memory bandwidth of ~150MB/s. Do you find this to be a limitation for the target applications?
The 150MB/s memory bandwidth quoted has to do with the Zynq FPGA design not the Epiphany chip or architecture. With the current Parallella architecture, the theoretical peak bandwidth is 1GB/s in and 600MBs/ out per elink. For compute bound problems or heavily pipeline algorithms, this is a pretty decent bandwidth. We are getting closer to reaching those numbers with the new Zynq FPGA redesign. Streaming 1GB/s does open up some interesting streaming applications in (decode, encode, transmit, receive, compress, decompress, encrypt, decrypt).
Impressive journey, thanks for sharing it with us. I was wondering weather we can build a small cluster (two boards as a start running RTEMS on 32 cores), using eLink cables? I googled it and found out it may be still a work in progress?
For now, you would need to use the Gigabit Ethernet port to cluster, but the arrival of the elink cables is now imminent. (finally!)
It would be awesome if the talk you gave was recorded and visible for people following the project, if it is, would you mind sharing the link to it =)
Would really like to see a video of this presentation!
Sorry, no video:-(
Why not write a book about it as both a biopic and educational material. Get filthy rich 🙂
I would be glad to write it up but it certainly won’t make me or anyone else filthy rich.:-)
That’s awesome!
I have worked with Tilera and CSX before.
Can you share applications developed on top?
Top application at the moment is wireless communication (ie SDR).
Just wanted to say what you have done is impressive as anything i’ve seen and I am working hard to bring applications to the Parallella and Epiphany. We will be at SemiCon West this July with a platform product that will make optimized application development for Parallella much easier. We will be open-sourcing software, putting out code bounties, etc. So for the love of technology…don’t give up!
Alex,
Thank you! Not giving up by a long shot and I am excited to hear that you are pushing ahead with your Parallella based program!! Can’t wait to hear more. Sorry if I have been hard to get a hold of…
Andreas
2nd week in April I’ll be in New York (RIT) with a videographer shooting some promo videos, including Parallella boards. Would be great if you could join us. Perhaps prepare another lecture and this time we can film it?
Sounds great. Send me an email with exact details/dates and I promise to respond.
Sweet! Doing that now. Sending email to support@adapteva.com.
We will be at Semicon West this July with a platform product that will make optimized application development for Parallella much easier.