New Parallella eLink FPGA project now available in Vivado


Last summer we started migrating the elink from Xilinx ISE to the new Vivado tools while also doing a complete overhaul of the design to improve performance, power, and maintainability. There is still optimization work to be done in terms of elink read/write performance, but I consider the new design to be a high quality starting point for future work. The new elink design project has been tested extensively at Adapteva and has recently gone through beta testing by friends in Sweden working on an exciting “non-parallella” Zynq + Epiphany board. More news on that development soon hopefully…

To anyone who has been stuck waiting for the new Vivado design, I am truly sorry for the delays! I am embarrassed that it has taken this long and I am doing everything I can to make sure this doesn’t happen again. A big part of this effort will be to more actively encourage contribution from outside Adapteva. Please consider this an open invitation to anyone with FPGA skills to contribute pull requests to the ‘parallella-hw’ repo. If you feel like there are barriers in the way, tell me how we can remove those. Together we can move faster.

The rest of this post is dedicated to getting you up and running with the elink and Vivado. For those of you who have never created HW before, this could be your first time:-)

STEP 1: Download and Install the Vivado software

You will need to follow the Xilinx instructions to download and install the Vivado 2014.3 suite. Start HERE.

Note#1: The download is large (>>1GB), be patient.
Note#2: Due to permission issues, it’s easiest to install it in it in your home directory.
Note#3: If you are running Ubuntu, edit the install script to use ‘/bin/bash’ instead of ‘/bin/sh’ (or change /bin/sh to point to bas instead of dash)

STEP 2: Download and unzip the Parallella project

$ wget
$ unzip

Note: Currently as of March 22 a headless 7020 project is available. (

STEP 3: Open the archived Vivado Project

Click the ‘open project’ and point to the *.xpr file inside the folder you just unzipped.


STEP 4: Run Synthesis

This step converts the Verilog RTL to a gate level netlist and optimizes the logic.
Find the right button to press in the GUI shown in the picture (or press F11).
(Ignore any warnings for now…)


STEP 5: Run Place and Route

This step maps the gate level netlist to the physical hardware inside the Zynq FPGA.
(Ignore any warnings for now…)


STEP 5: Create the raw bitstream

(Ignore any warnings for now…)


STEP 6: Tweak the bitstream

There may be a better way of doing this…and if there isn’t there should be!! More than once I have forgotten to do this and gotten the error message: “Error: Timeout waiting for FPGA to config.

a. Create a file called ‘bit2bin.bif’ with the following content

b. Make sure you have a dummy.elf in that directory. You can copy use this one.

c. Run some “magical steps” using the Xilinx tools to convert the bit stream to a loadable bit stream.
$ source $XILINX_INSTALL_PATH/Xilinx/Vivado/2014.3.1/
$ bootgen -image bit2bin.bif -split bin

STEP 7: Copy the new *.bit.bin file to the boot partion of a Parallella SD card.

Note: Sync and properly eject the sd card as appropriate for your system.

STEP 8: Boot the system.

Run some tests and report back if you have any issues.


  • Anssi says:

    Looks like it’s a pretty good idea to install Vivado 2014.3… With the current version 2014.4 I needed to update a bunch of IPs first and then synthesis still didn’t run. It did something for a while but then nothing was happening.

    2014.3 worked fine. Also it seems to be enough to install just the “Vivado Design Suite WebPACK Edition” with Software Development Kit which makes for about a 3 GB download total when using the “Vivado and SDK Standalone 2014.3.1 Web Install Client” thing.

    One last thing, your link to the dummy.elf isn’t working so generating the final .bin file with bootgen isn’t going to work with the instructions here. And anyways, I don’t have a 7020 based board but I guess the design will work on a 7010 as well if I change the target chip in Vivado?

  • John says:

    These instructions worked fine for me with version version 2014.4 although the location for the dummy.elf file has moved:

  • Bedoustani says:

    The project is OK with Vivado 2015.1 too.

  • Bedoustani says:

    The timing error between eclk_pll and cclk_buf is because BUFG maximum frequency for the xc7z020clg400-1 is “464Mhz” and PLLE2_EDV generate 600 Mhz. However it is working properly. (If you repeat the implementation for the “xc7z020clg400-2” which has BUFG maximum frequency of “628Mhz” and it complete successfully.)

  • maxy says:

    It almost works with Vivado 2015.1 too. After upgrading the IPs in the block design, there was a mismatch in the address size from axi_bram_ctrl2 to eCfg_0. Quick workaround: expand the interface and connect the bram signals individually. Got a warning about the highest address bit not connected, but the bitstream works.

  • Jeff says:

    My goal is to borrow from this design to enable the Parallella board with Matlab’s HDL development tools. I am starting by getting this design to generate.

    For Vivado 2015.2, I let Vivado update all of the IP components to the latest version. When right-clicking on the elink_testbench design window and running “Validate Design”, I got three critical errors. I was able to clear these errors and then the design passed through Synthesis with no critical errors. Here is how I cleared these errors:

    — In elink_testbench, I double clicked “blk_mem_gen_0” and changed “Mode” to “BRAM Controller”
    — In elink_testbench, I double clicked “blk_mem_gen_1” and changed “Mode” to “BRAM Controller”
    (save changes!)
    — In elink2_top, I right clicked “eCfg_0” and selected “Edit in IP Packager”. (The goal is to set the custom IP to also use the MASTER_TYPE mode as “BRAM_CTRL”). In the Sources window, open the IP-XACT folder and open “component.xml”. In the new window select “Ports and Interfaces”, right-click “mi” and select “Edit interface…”. In the new window, select the Parameters tab. Add a new bus parameter called “MASTER_TYPE” and set its value to “BRAM_CTRL”. Save the project and close it, and rerun the IP Status report (under Tools) and re-update the eCfg_0 IP so the changes are reflected in the top level design.

    After making those changes Validate Design give no critical errors, and Synthesis also runs without critical errors.

    (This help topic helped me get here:

    • Jeff says:

      To update my earlier note, I have tried upgrading the original project to 2015.3 and it was successful following my previous note with one change. After adding the “MASTER_TYPE” parameter with value “BRAM_CTRL” to the “mi” bus and closing the IP Packager, Vivado does not seem to automatically notice the IP for the eCfg_0 block has changed. The IP can be forced to refresh by right clicking on the “eCfg_0” block in elink2_top and selecting “IP Settings…”. In the new window select the “Repository Manager” tab, then click “Refresh All”. Then click “OK” to return to the elink2 design, and then rerun the IP Status tool and complete the steps as in the earlier note.

      • Jose M Monsalve says:


        I was getting the same issue, I got to solve the two of the elink_testbench by myself but I was struggling with the one on elink_top.

  • Dan Johnson says:

    I’m running the configuration below and am unable to open the final target device. I don’t see any hardware in the list like I do form my MicroZed board. I’m new to Vivado but have been successful using debug cores and the simulation tools on some failry complex designs. Any suggestions?

    Vivado v2016.2 (64-bit)
    SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016
    IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016

  • BGeorge says:


    I am beginner with parallella and I study to make a multi heterogeneous processor and the ability to use zynq and epiphany is tempting. If i have the ability to use also fpga board to import a soft core parallel with zynq and epiphany this is awesome.
    Could you explain more what is the eLink’s behavioural ?
    Also if it is possible could you present a block diagram of the parallella hardware of the above implementation?
    With eLink you achieve the communication between zynq processor and epiphany ?
    Finally with this parallella hw (after that implementation) have I the ability to install operation system?
    Apologize if my questions have answered somewhere else. I have not found something clear at this time.
    Continuo your good job!!

    • BGeorge, you might look into the work done for GSoC for the RISC-V core. All the hard bits are already in place to get that running in the PL (FPGA part of the Zynq), along with the eLink.

      Elink is a way for the ARM/Linux side of the parallella to interface with the Epiphany, usually using shared memory.
      If you use the pre-built images for the Parallella, it includes the FPGA bitstream for the eLink, and some examples you can use to test the Epiphany and see how to program for the environment.

      “Can I install an operating system?” is a bit of a tough one to answer. You can install Linux quite easily on the ARM side of the Zynq without any FPGA configuration, but you will probably want something to let you get network connectivity, video output, etc. As for installing an OS on a soft-ip core like a RISC-V it’s totally doable, but that core doesn’t show up like another CPU in a “normal” multicore x86 computer. All input, output, storage, etc has to be implemented as if it were a totally seperate device. The GSoC project has more info on this. As for installing an os on the Epiphany cores, I think some people have gotten some embedded kernels to run, but with 32k of local memory per Epiphany core, don’t expect to have something like the Linux kernel in there. Getting something resembling a traditional OS is totally possible, but would require a lot of work and probably isn’t what you want anyways.

      The Epiphany is more of a way to move tasks that can take advantage of a parallel architecture away from the 2 main ARM cores.

      Hope it helps,

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