Creating an FPGA accelerator in 15 minutes

parallella_zynq

The best kept secret of the Parallella board is probably that it includes a very capable FPGA from Xilinx.  Until now, the FPGA has not seen significant use due to the big time investment needed to get started. I have created a small “hello world” toy example targeted for anyone interested in hardware design. The simple design includes a 32 bit adder accessible as a slave component on the ARM AXI bus. For more details, see the presentation and source code below.

Presentation (PDF) 

Code (github)

Shortcut (if you are in a hurry…):


$ git clone https://github.com/parallella/oh
$ ./run.sh accelerator
$ gtkwave waveform.vcd # view waveform

$ emacs src/accelerator/hdl/accelerator.v # "put code here"
$ cd src/accelerator/fpga
$ ./build.sh # build bitstream
$ sudo cp parallella.bit.bin /media/$user/boot # burn bitstream onto SD card on laptop/desktop
$ sync # sync and insert SD card in parallella

Using this example you should be ready to create your own unique Parallella flavored hardware in less than 15 minutes.*  As always, feedback is appreciated.

Cheers!

Andreas

Andreas Olofsson is the founder of Adapteva and the creator of the Epiphany architecture and Parallella open source computing project. Follow Andreas on Twitter


[*] Assumes you have Vivado tools installed. If you don’t have them, you can get them for free HERE.

20 Comments

  • Creating FPGA accelerator is a bit cumbersome if you don’t know what is an FPGA and if you want to stick to historical flows (RTL). That’s why XILINX developped Vivado HLS (High Level Synthesis) that transform C-code into HDL. But you still have to master the backend flow (from HDL to bitstream to run on the FPGA). The next step that is publicly available since July 2015 is called SDSoC: Software Defined System on Chip.
    You create your complete system in C/C++ and then select the functions that have to be implemented in hardware. SDSoC will call Vivado HLS in the background to create the RTL code, and then will connect these accelerators to the processor (SDSoC is available only for Zynq devices containing a dual Cortex A9 + programmable logic region) or any other available connector… the AXI4 connector of an epiphany chip for example. The Parallella board is not yet (up to my knowledge) supported by SDSoC, but it would take a few hours to create one and then make it available on this website so that anybody with an SDSoC license could create complete system using the 3 computing elements of the parallella board: Epiphany chip, ARM Dual Cortex A9 and the FPGA side.

  • Since it should only take a few hours, perhaps you or someone else at Xilinx could create the SDSoC support files for Parallella?

    I am sure our 10,000 Parallella users would be very grateful.:-)

  • Alan Rocker says:

    I was in a conversation about implementing Perl 6 on your board, since the language has built-in features for parallel processing when the FPGA came up. The other person thought that it would require something like VHDL and the FPGA to get the use of multiple cores. I originally thought that you had used it to create what would look like an ordinary multi-core machine to the user, but on further investigation, I think the FPGA is an optional feature that the informed could use to implement special instructions, and the naive could ignore.

    Where in that fog of misapprehension is truth to be found? :-)*

  • […] initial thermal testing, it does look we have solved the problem. I used the case to showcase the FPGA accelerator project at Argonne National Laboratory a few weeks back and I can tell you that it makes a world of […]

  • Keith Sloan says:

    Why does the presentation say the cost of failure with HW is HIGH?
    I was under the impression that with FPGA’s that the state gets loaded from an SDCARD or some such.
    i.e. If you make a mistake you can just reload.

    Is there some risk one can damage the FPGA by say feeding 5v to something that only tolerates 3.3v?

  • Andreas says:

    I was under the impression that the FPGA resources on the Zynq were used to implement the glue logic with the epiphany chip. Is this assumption wrong? Are the FPGA resources available to use freely for whatever kind of function a user wants?

  • Leon says:

    I wanted to create a pl acc in parallella before with hls but failed, because I didn’t know how to integrate my hls ip core in the parallella zynq hw project and how to use it in software. I will try the sdsoc.

  • Brendon says:

    Your
    Presentation (PDF)
    Code (github)
    links are broken (gives 404 errors)

  • derek says:

    links are still broken

    • Was fixed, but the directory structure moved again. Now fixed again…

      • I’m considering using a Parallella board running some flavor of Ubuntu, and I want to use the board to interface to a CMOS camera sensor. I’m connecting the camera sensor to the Zynq-7000 through the GPIO pins. I want to grab a frame of video into the FPGA and then transfer the data to the CPU side as quickly as possible. If I was using the MicroZed or Zed board, I would use Xillybus to handle this transfer. How do you suggest I do it on the Parallella?

  • Idan says:

    I don’t get it, why do you say it takes 15 minutes if synthesis by itself took 2 hours ?. So basically the FPGA part is useless without non-free software (like Vivado) till this day?

  • This is a intersting code with FPGA. Thanks for sharing this code with us.

  • marcelo says:

    I did not like W3 Total Cache I use super cache wp

  • anderson says:

    very good this site, I will share with my friends.

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