MyriadRF + Parallella: First steps

The application I have in mind for my future Parallella board is to use it for various software-defined radio (SDR) applications. Given the small form factor, low power and high computing power of the Parallella, it would be ideal for a wide range of embedded uses. I can imagine portable battery powered units that are always ready to explore the spectrum around you, or even radio remote heads where you just place the radio and antenna in some remote location and only access it via network, with the bulk of the SDR work being done on the board itself and only sending back the data payload rather than raw radio samples.

To accomplish this, the first problem is to bridge the RF world with the digital one;  some way to convert radio waves into digital samples and vice versa.

Of course, there are several solutions that could be plug-n-play, like rtl-sdr sticks, HackRF, BladeRF, UmTRX, Ettus USRPs and so on. But all of those are primarily meant for PCs and they use standard PC interfaces like USB or Ethernet. In all of those, some significant part of the hardware is actually there only to drive those standard interfaces! In the Parallella, there is a FPGA, and exposed are 48 high speed GPIOs that can be programmed to do … well … anything, and implement any kind of native IO protocol a radio front end might need.

This is where the MyriadRF comes in. This tiny board is sort of a demonstration board for the LMS6002D RFIC. It’s designed by Lime Microsystems themselves and it’s also fully Open Hardware. This particular chip is pretty great: it’s essentially a full duplex radio in a chip, capable of receiving and transmitting up to 28 MHz bandwidth signal anywhere from 300MHz up to 3.8GHz. And to top it off, the manufacturer has a very friendly attitude towards OSS and OSHW, with all documentation for the chip freely available (see here), a mailing list to discuss issues and they sent me a board so I could work on this application (Thanks Lime Micro 🙂 ).  So it’s no surprise that a good number of new SDR hardware products based on it have popped up recently.

So, to come back to the topic at hand : how to use this MyriadRF ?

The board basically exposes the raw digital IQ interface of the LMS6002D chip, a SPI control port, a few GPIOs to control RF switches and some clock inputs. The clocks will have to be fed from some clock generator ICs (for various reasons, like phase noise, it’s not especially a good idea to try to feed these from an FPGA). But all the other ports could be plugged directly to FPGA IOs. When the time comes to actually design a daughter card, the GPIOs and SPI might be connected through I2C to leave more FPGA GPIOs free for other things. And with the final Parallella some level conversion will be required as well since the MyriadRF is 3v3 logic while the PEC_FPGA IOs are 2v5.

But all that is for later. I wanted something I could test NOW, with the Myriad RF I have and the Parallella prototype that is based on a ZedBoard. You can see below the setup I came up with. Basically I used the DE0-nano carrier board which is designed for the Myriad RF and it conveniently breaks out all the connections to the MyriadRF to standard .1 inch headers. It also includes a Silicon Labs clock generator IC. So far I have limited myself to the RX side and just wired all the data lines to some of the ZedBoard PMODs — the only thing to pay attention to is to connect the RX clock to a clock capable pin. As for the control lines, they’re currently driven by a Cypress FX2 on-board the DE0-nano carrier board, and controlled from the Parallella through USB. In future versions they’ll be driven directly from the FPGA, but as I said, for now I’m focusing on getting something running.

Test setup of the MyriadRF with the Parallella prototype

With the electrical connection done, the FPGA programming part could begin. Again in the spirit of getting something running quickly, I coded a simple interface to capture the samples and push them into a FIFO. The next step was to get them out of the FIFO and into the DDR with some block controlled from the ARM. For this part, I cheated a little and used a Xilinx tool called Vivado HLS which allowed me to write a quick-and-dirty AXI bus master in no time. The bad news is this tool isn’t available in the free WebPack edition of ISE, so I’ll probably rewrite that part in pure HDL to get more control and also allow a wide audience to rebuild the code.

Once all that was done, I could finally try to get some samples into the DDR and access them from the ARM. Currently there is no driver to speak of — just a couple of memory mapped control registers. And it doesn’t even allow a continuous gap-free stream, it just reads a few millions samples and places them into RAM. But this was enough to grab a couple of seconds worth of data and feed them to GNURadio to see the GSM carriers in the vicinity :

GNURadio showing captured samples of GSM activity

So what now ?

Well this is only the beginning. The HDL code has to be improved, a lot. A daughter-card has to be designed. A proper driver has to be written. A good way to ship all those samples to the Epiphany has to be found, possibly bypassing the ARM altogether. Much work left to be done 🙂


  • Sylvain,

    An impressive start, especially considering the challenges you faced as an early user! Can’t wait to see how the project turns out. Note that in the latest version of the schematic, the VDD_GPIO is adjustable from 1.8V to 3.3V through I2C. Let me know if we got it right.:-)


  • Tuppan says:

    * ! *

    Great! Nice!


  • Andrew Back says:

    Michael Ossman’s HackRF is an extremely cool piece of hardware and I know there are a number of backers looking forward to using theirs with Parallella!

    It’s fantastic that interest in SDR is really picking up and there is a growing selection of affordable hardware platforms available, each with their own particular strengths.

  • I really hope that someone does come up with a Parallella adaptor for the BladeRF because I received mine this afternoon and my PC is compiling GNU Radio right now. The BladeRF shouldn’t be discounted so easily because it has a high speed IO interface to the FPGA which could easily be used for this and it doesn’t have to depend on the USB3 interface. That said the USB 3 interface could even be used to interface to the Parallella via the high speed IO!

    Lots of potential!

  • Andrew Back says:


    Agreed, I’d love to see high-speed integration of Parallella and BladeRF. There will be plenty of BladeRF boards out there and it’d be great if there were a simple solution for those who wanted to use theirs with Parallella.

  • Sylvain Munaut says:

    @Bob, well, there is a lot of extraneous stuff when connecting the bladerf to the parallella. I mean you have 2 FPGAs and the FX3 would be unused …

    But if you insist, I think the best option would be to design some flex cable with samtec connectors at both end and make a bunch of fast lvds channels. Custom flex aren’t cheap in low qty though …

  • Cintya says:

    Bryan, that is an interesting thohgut about using Kanban for managing the Definition of Done (DoD). I am only mildly knowledgeable about Kanban so I would have to do some reading and thinking to see if this is a valuable way of managing things.While this should be a simple concept, it took our team a while to get it . The DoD and Acceptance Criteria (AC) are not the same thing. We were using the terms interchangeably and it did add to some early confusion in the team. Once we did get it, we realized that the DoD is, in general, identical for each story. I say in general because there can be some exceptional cases, but those should be minimized. The AC, however, is unique for each story. Demonstrating, or testing, or verifying, or whatever you call it, confirming that the AC has been satisfied is one item on the DoD.For now we manage the DoD as a simple checklist. I won’t give our exact DoD but you can envision it is something like this:- Design code submitted into release branch- Verification code submitted into release branch- All code passes lint checking and defects have been corrected- All code has been inspected and defects have been corrected- All tests for the story pass dynamic simulation and confirmed with Functional Coverage.Note that the tests and Functional Coverage align with the AC.- The submitted code has passed at least one overnight regression suite, including extensions made for this story (new stimulus, widening of constraints, plus all previous stimulus).- The AC has been demonstrated on target h/w (easier to do this with FPGAs than ASICs).-So if it is a simple checklist, it may not be necessary to manage this with Kanban. I would have to give this further thohgut, however.The AC is unique per story. Other than asking if the AC has been satisfied, our DoD list does not track AC specifics. Rather we track this in our verification plan for simulation, and can confirm that the AC has been satisfied with the simulation scoreboard and transcript, plus the Functional Coverage report. All the simulation artifacts are automatically saved and are accessible via a Wiki page. For tracking that the AC is satisfied on target h/w, we are currently using a manual spread sheet although we are looking into a Wiki format for this as well.Cheers Alan

  • Adam says:

    A couple of quick notes:1) User Stories were orilgnaily just called Stories in Extreme Programming, as in Tell me a story about what this system is supposed to do. 2) The As a format actually originated with a project at a now defunct company called Connextra in the UK in 2001, and was popularized by Mike. It isn’t, however, the only way you can write stories!James’ suggestion is a very good one, and holds to the intent of stories that they should focus on the business purpose rather than the technical one.Another view is that you can substitute Actors for the Role if you have come from the Use Case world.

  • That’s an inventive answer to an interesting question

  • So that’s the case? Quite a revelation that is.

  • Such an impressive answer! You’ve beaten us all with that!

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