by aolofsson » Tue Apr 02, 2013 7:04 pm
Sylvain,
That lclk divide program should be considered a temporary patch, because the link from the Epiphany to the Zynq currently does not work up to 300MHz. We need the divide by 4 to get the link clock down to 150MHz.
The rc_local method was not ideal, we are just now in the processing of putting that patch in the system reset sequence code. Obviously the plan is to get rid of it all together once we have the system ramped up and running.
Thinking of it now, if you were resetting the board during your work without power cycling the board, then the lclk divide settings would have been deleted, and could lead to the issues you were seeing with the DMA...
Andreas