Parallella Reference Manual Release

Now that the Parallella board design is finally stabilizing we are ready to release rev-zero of the Parallella Reference Manual (PDF). This document should be considered an initial rough draft and there are bound to be some typos and mistakes (only a few eyes have reviewed it so far). We felt it was important to get the information out to you as quickly as possible for review and hope you will forgive us (or filter out the errors automatically while reading as I do).

We need immediate feedback in the following areas:

  • PEC_POWER/PEC_FPGA expansion connectors. Please tell us if there were features in the specifications that aren’t really that useful. In addition, of course please tell us if there are features missing.
  • Choice of the Samtec expansion connector.(mechanics, expansion card applicability, and ease of use)
  • Placement of expansion connectors on the bottom side of the board?
  • What kind of daughter cards do you want to see? (breakout board, loop back board, etc)
  • Missing or unclear documentation for key board features.
  • Anything else?

At this point we feel pretty good about the design, but if there are strong and valid objections to our approach, we will definitely listen to make sure we get the design right.

In addition to the Parallella manual we have also decided to publish the Epiphany-III Datasheet (PDF) so that you now have open information access to all major ICs on the Parallella board. (There is still one IC on the board that requires an NDA for datasheet access, but the vast majority of users won’t care. We are hopeful that the company that makes this particular IC will eventually open up the datasheet to the public).

In our mission to deliver the Parallella open computing platform will be to publishing the Epiphany SDK driver and library sources to github by the end of next week. (In case you hadn’t noticed, the sources for the Epiphany SDK and OpenCL SDK from Brown Deer Technology are already available on github).

17 Comments

  • elecnix says:

    Datasheet PDF has “Error! Bookmark not defined”

      • Anonymous says:

        Two small remarks:
        1. As the Parallela-64 and the -16 board uses diferent subLVDS voltages, how about the VDD-ADJ is it different also (2.5V and 1.8V ?) or can you provide a key, so the connectors cannot be mixed or set both voltages to a different pin–
        2. Maybe you can provide a small temperatur sensor on the board close to the fpga (if there isnt any ont he chips itself), just to get a rough board temperature for larger systems its helpful to find hot spots (in racks …)

  • Two small remarks:
    1. As the Parallela-64 and the -16 board uses diferent subLVDS voltages, how about the VDD-ADJ is it different also (2.5V and 1.8V ?) or can you provide a key, so the connectors cannot be mixed or set both voltages to a different pin–
    2. Maybe you can provide a small temperatur sensor on the board close to the fpga (if there isnt any ont he chips itself), just to get a rough board temperature for larger systems its helpful to find hot spots (in racks …)

  • Fabio Utzig says:

    On the first paragraph: “The Parallella-16 with a16-core”. There is no space between “a” and 16-core.

    On the features table: “The Parallella-64 board includes the 64-cire”. It should be 64-core.

    On performance table: “800MHz(Parallella-16”. It’s missing close parenthesis.

    “The standard connectors on opposite sides of the cards to allow” should probably be “The standard connectors on opposite sides of the cards allow…”

    “diameter mounting holes in the each corner” should be “diameter mounting holes in each corner”

    Also regarding this sentence: “The Hardware Description Language (HDL) source code for the eLink and remaining logic will be available as free open source code once the final Parallella boards ship.”

    Why release later when it could be sooner? 😉

  • Rob Scott says:

    Presumably, you’ve looked at the FMC – http://www.xilinx.com/products/boards_kits/fmc.htm which is as close to a standard for FPGA boards as we get 🙂

    Also, the Zed board (another Zynq 7020 board) has had some power supply problems, so you may want to compare/contrast the Parallella design to it.

  • veqtor says:

    I find the Samtec headers a bit hack-unfriendly in that it’s harder to diy shields with them, but I do realize their value in high-speed applications. Do you plan on releasing a docking-board with IDC headers?

  • V Bain says:

    Bring Zync reset signal to Power connector?

  • Graeme Houston says:

    Gewtting like raspberry pi launch, when can i get a board, i missed the kickstarter as bbc news does not understand the benifit if advising of exiting things like this until after the event, so was unable to participate at kickstarter level

  • Just looked at the power connector PEC_POWER,
    SYS_5P0V 1 2 SYS_5P0V
    I2C_SDA 3 4 UART_TX
    are very close, it would be great to put a GND inbetween oder a N/A and shift all down one row. A short between 5V and on of I2C or UART might kill the Znyq (if directly connected?) — this can happen on testing new add on boards very quickly by a solder fault. I think the other power pads are not that critical.

  • V Bain says:

    Another suggestion for the Power connector..!
    Bring 5v power in through this in addition to through the power jack. (I know you have the output of the USB/jack selector available, but I don’t think feeding current IN this way would be a good idea for the power mux IC?).This way multiple boards could be powered neatly from a baseboard.

  • […] is finally stabilizing we can release rev-zero of the Parallella Reference Manual. Here is the blog post describing the document release. In the same post, we also published the Epiphany-III data sheet […]

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