is now up - this provides instructions on creating/connecting an IP Core using the AXI4 interface to communicate with the ARM. This is more suited to a larger chunk of memory (BRAM), compared with the limited register set based approach seen last time with AXI4Lite.
Not particularly exciting in and of itself - but certainly if you have an idea of what you want to do with it, you have all you need there.
I realise I need to write up the sequels for Tutorials 1 and 2. I have taken these further, but put them down about 2 months back (I have been busy writing tutorials, migrating to a new hosting solution, and porting FuseSOC). For AXI4Lite, I threw together a (very) basic ALU. For AXI4, I implemented an image smoothing algorithm.
So I will revisit these projects, get them into a reasonable state, and make an instructional tutorial for each. With these will come python scripts for on-target testing, as that is what I use myself during development. Loading in pixels one at a time is for suckers
![Smile :)](./images/smilies/icon_e_smile.gif)
Beyond that, I might investigate / cover a better tool for loading arrays of data into/out of the FPGA / reading back. The tool I've appropriated to date is really not suited to the task. After that? Nothing planned as yet. Hopefully AXI4-Stream when I have it working - but haven't been looking into this for a good month or more.