Parallella FPGA Tutorials available

[yanidubin]

Hi all,

As some folk have been requesting it, I have released the first of my Parallella FPGA Tutorials over at .

These are aimed at people wanting a leg up with FPGA design on the Parallella. I assume knowledge of driving the Xilinx tools. They are written by a hobbyist - I am not an FPGA developer, and by no means an expert. I have digested this knowledge from manuals / other tutorials written for other Zynq based platforms. These are heavily tailored to the Parallella to ease you into things, making this more accessible. I don't intend to write many, since I feel once people have worked through these, they are better off going forth and learning from the many great tutorials out there which need some adapting to this great platform.

Feedback / requests welcome, which is why I've created this thread. This is my first blog / public tutorial - please let me know what I can improve on (other than brevity - that is a lost cause I fear). There is only so much I can do about presentation as I'm rather hampered by using free WordPress (I read it was great and customisable - sounded perfect. Then I discovered you don't get that, or even javascript, unless you host it yourself, and I do not have any hosting available).

The list of Tutorials which I'll keep up to date in this first post are:

Tutorial 0 (part 1) - setting up a new project / repo
Tutorial 1 - using AXI4Lite to communicate with the FPGA from the Arm

Next on the list is Tutorial 2, which will cover full AXI4, and reading/writing from BRAM so that your core has access to significant temporary storage (for matrix and image operations).

Eventually, I hope to get AXI-stream going, which is a high performance DMA driven interface. If I do, I'll write a tutorial on that too.

[aolofsson]

Hi Yani,

Fantastic tutorial!! Impressive how quickly you pulled it together! I would recommend displaying the images of the screen shots instead of having links (just my two cents:-)).

Now for my view of the world...I am not a big fan of GUIs. The only times I used them for chip design was to generate/configure a piece of IP or to visualize some layout. Otherwise, everything was scripted in tcl.

Many hackers/developers probably want to learn as little as possible about the ins and outs of the Xilinx IDE and flow and just want an entry point for experimenting with hardware design. A goal is to develop an "all text entry" sandbox, where folks can add some hardware without mucking around with all the config/build stuff in Vivado/ISE. The sandbox would include an AXI interface, some way of writing/reading to the block. (clearly more details need to be worked out...)

The development loop would be:
-Edit a Verilog text file "enter code here".
-execute a build script "make"
-run/test on board

I am sure a lot of software developers would get a kick of writing some Verilog code, but the barrier to entry needs to be reduced to zero.

Thoughts?

Andreas

[AndyC]

Hi Yani,

Thanks very much for the tutorials, very useful.

Cheers

Andy

[yanidubin]

Hi Andreas,

Thanks I am on leave this week, and this seemed like a good use of my time - but I'll go a bit quieter I daresay. And the sun is out, so time for springtime photography.

I'll certainly give that some thought. I completely agree with you, and would like such a workflow myself.

I moved my replies to so we can flesh this idea out.

Regards,
Yani.

[9600]

On the matter of being freed from the GUI and having a nice console-based build system, just posted about .

Cheers,

Andrew

[yanidubin]

A new tutorial should be forthcoming in the next few days, as I have successfully routed UART0 via EMIO to external pins (replacing GPIO assignments), and looped these back using the header on the Porcupine which arrived yesterday (thanks Adapteva - you guys rock!). This has allowed me to verify it is functioning correctly, and routed as intended (I don't have an oscilloscope at home).

So Tutorial 003 (I've left a spot for the full AXI4 tutorial which I still plan to provide) will cover all of this. I intend to provide this as a visual guide as per the previous ones, as well as raw diffs (because the inner workings are important to understand here - and if you don't want to use the UI, well then you don't have to).

The process covers the PS setup (enable/export peripheral), system_stub modifications, pin configuration in the constraints file, wrestling control of the pins from the gpio_emio module, and the devicetree bits - having done this, you should be ready to connect whatever mix of peripherals your project requires.

Guidelines on interfacing GPIO to higher voltage domains are also forthcoming - I have started a discussion on this .


PS: If you're rearing to go with this, know what you're doing, and don't want to wait for the write up, I decided to push to GitHub already - so you can find the project in the .

[yanidubin]

is now up as promised. I think the only thing missing is a photo of the Porcupine showing where to place the jumper - I will add one at some point. Feedback as always is most welcome - please let me know if anything is unclear.

[aolofsson]

Yani,

Another great post! The breadth of knowledge that you have is impressive! One of the challenging things about the zynq is needing knowledge about software (linux etc) and hardware to get started with some of the really interesting features. I really like how you wrote down every step in detail (not just writing "compile the device" tree). This will help a lot of people who might be experts in one domain but novices in another.

(ocd alert, what happened to tutorial#2? )

Andreas

[Mukti]

[yanidubin]

Thanks Andreas,

My breadth (rather than depth) of experience here lends itself well to this style of "getting up and running" tutorial, regardless of which area people are coming from. You make a good point, and I will certainly try to keep this up.

I came in aiming to brush up on my SoC/Linux/HW skills mostly - but being a generalist, diving into the FPGA aspect proved too tempting Although I didn't realise it at the time, the current lack of a pinmux implementation would have necessitated going down this route anyway (interfacing with daughter-boards being on my horizon for the camera robot project).

Tutorial 2 will be along eventually - I've reserved the spot for using the AXI4 interface, to complement Tutorial 1 (AXI4Lite). I have had this working for some weeks, and will get around to it eventually

Yani.