Hi Guys,
I have managed to add AXI peripherals using XPS on the hdmi project and everything works fine.
When I do the same on the headless project though I get the following critical warnings:
[Constraints 18-11] Could not find cell or net 'axi_interconnect_1/*_converter_bank/*clock_conv_inst/*asyncfifo_*/*mem/*dout_i_???' [C:/Development/parallella/Fpga/parallella-hw/fpga/edk/parallella_7020_headless/implementation/system_axi_interconnect_1_wrapper.ncf:6]
[Constraints 18-11] Could not find cell or net 'axi_interconnect_1/*_converter_bank/*clock_conv_inst/*asyncfifo_*/*mem/*dout_i_????' [C:/Development/parallella/Fpga/parallella-hw/fpga/edk/parallella_7020_headless/implementation/system_axi_interconnect_1_wrapper.ncf:7]
If I run through the implementation and generate the bitstream it loads ok but when I try to read from the AXI bus from a linux app the parallella hangs totally, so I guess these warnings are important
I have been banging my head against the wall for a couple of days over this, does anyone have any pointers of where to look to find the problem?
Thanks
Andy