ARM/FPGA AXI DMA xfers using Parallella-adi kernel

[yanidubin]

Has anyone managed to get DMA transfers (either 1D or 2D) to/from the FPGA working well? In particular AXI streaming DMA - but I'll consider other working alternatives.

I have been playing around with AXI peripherals synthesised in the FPGA over the past few weeks. I have had success with both AXI4LITE and AXI4 via the memmap interface, and having the FPGA do ALU / pixel type operations, but no success yet with high performance memory transfers.

Ideally, I'd like to test DMA performance using a pre-existing kernel driver rather than diving in and writing my own straight away (I'm brushing up on my VHDL, specifically, at present).

I have had very little success with streaming DMA. I have a VHDL module synthesised to use this interface, but trying to interface with it under Linux from the ARM side is proving to be a problem. All the Xilinx provided examples seem to be based on a baremetal application. The most helpful I found was for the Zedboard, and relied on the . In particular, . While I have built this against the Parallella kernel, it triggers a kernel panic - I believe the particular driver it is trying to bind with (Xilinx AXI DMA) may be missing/different.

I haven't yet built the Xilinx kernel for the Parallella - but if you have, and have any hints, those also would be appreciated.

Or, if you know how to get DMA going (FPGA, not Epiphany) on the Parallella-ADI kernel, I'd like to hear from you. Getting it running on Xilinx is just a temporary measure, as long term, I want to be able to generate something (bitstream, devicetree if necessary) which anyone can use on their Parallella - so ideally something which works on the Parallella kernel (and default config would be a bonus here). But if I can get something working on Xilinx as a starting point, I can potentially port across the driver at a later date.

[theover]

Well, uhm, there is the ARM_to_Epiphany interface, which uses DMA up to a few hundred MHz.

[yanidubin]

I am aware of that interface, but not sure that this is of any help.

A few weeks back, I looked at the memory interfacing for the matrix multiplication example (e-matmul16?), and if memory serves (pun intended), the Epiphany SDK (in this case at least) works by reserving a portion of memory (I seem to recall seeing it in the devicetree), and writing the data for the Epiphany to this region after a memmap call, so it is where the Epiphany expects to find it. The Epiphany then uses DMA to read/write data to/from this location. Finally, the ARM reads this from DDR. I don't believe I found any DMA transfers initiated from the ARM side at all.

I may be wrong, but at the time I concluded from my quick glance that there was no DMA controller in use here which was common to the FPGA. But I didn't do a thorough investigation of the various other examples.

What I am specifically after is DMA for the AXI interface between ARM and FPGA - I'll edit my post to make this a little clearer.

[peteasa]

Seems like this should be an easy thing to do. But Xilinx dont half make it difficult!

My present effort adds a AXI4-Stream interface (documents in ug761_axi_reference_guide) plus the axi_dma LogiCORE (documented in pg021_axi_dma). To get the DMA hooked in you configure three additional High Performance AXI Slave ports in the System Assembly View so that you can connect Scatter Gather, MM2S and S2MM stream interfaces. Then Xilinx kicks in because the busses are not connected for you and when connected the pins are not connected and then you get warnings about reset on the stream interface being trashed late on in the netlist creation. I fixed this by removing Auto on the DMA Common Primary clock and forcing it to be Asynchronous and also added Data Realignment Engine to the MM2S and S2MM channels. So now I should be able to get a bitstream..

The kernel driver you point too seems not to hard to tackle next. The test should be quite simple, dma data from one place to another and send a few bytes from the processor over the streaming interface to memory. Let me know if you have made progress with this project! I have not simulated the fpga in anyway so there is a good chance it wont work for me!

[yanidubin]

No, I have not looked into this again, too many other projects on the go. I didn't encounter any of those issues generating the bitstream, and getting the driver built against the Parallella-adi kernel was also straight forward. But then I had an access violation when loading the driver module. I did not debug the issue any further, but expect it was support lacking in the Parallella kernel which was present in the Xilinx kernel.

Good luck, and let us know if you have any success with this

[peteasa]

[peteasa]

I have published my environment now. Because I have updated to elink-redesign I have not yet re-run the AXI DMA xfers example but at least you can see all the code in its glorious detail in the examples/kernel/xdma_lib from the examples submodule in https://github.com/peteasa/parallella.git