Matrix multiplication on PARALLELLA IV

[mhonman]

I've just come across a paper from Paralant describing their Insight library for Epiphany, that contains a super description of how to get the best from the Epiphany architecture, and includes measured speedups for various matrix sizes on a 16-core Epiphany at 1GHz/core.

The bottom line is that it tops out at 7Gflops for multiplication of 64x64 matrices - not at all shabby! [edit: as pointed by EggsBackonandSpam below, that is on just 4 cores]

This paper is very well written and could be used as a tutorial on getting the best from the Epiphany architecture.

[shodruk]

Clearly, the bottleneck is in external memory access.

[EggBaconAndSpam]

I beg to differ.
First of all, they are actually using 4 cores, not 16, therefore 7GFlop/s at 1GHz correspond to a 90% efficiency.
Secondly, for sufficiently large matrices, the operation is bottlenecked by the computation part( O(n^3) ) as opposed to the bandwidth/network.

[shodruk]

Excuse me. I should have written "off-chip memory access".
I'm thinking about why they had to restrict up to 64x64 matrices.
However, 90% efficiency is great.

[mhonman]

What I felt to be particularly cunning in their approach is to take advantage of the large register file, breaking the big matrix into smaller ones that can be multiplied in registers only (compared to the Adapteva example where the smallest matrix is sized for internal RAM).

I think though that there is no element of staging matrix chunks between internal and external RAM, as 3 64x64 matrices will fit into the internal RAM of 4 cores. It would be interesting to know whether the Insight library product runs up to the 512x512 arrays that the Adapteva demo can handle, and how performance scales once the matrices cannot fit into Epiphany internal RAM.

[shodruk]

I suspect their library couldn't handle 512x512 matrices at that time.
Because Parallella's off-chip memory bandwidth is rather low as compared with its high computational horsepower, I think the key factor of optimization technique for Parallella is to minimize off-chip memory access.
And, it should be very hard.....(but fun!)

[mhonman]

[shodruk]

[sriranjan]

Could someone point me to the exact code (library and example) for matrix multiplication using the 16 core chip like yaniv showed in the video.

[ubii]

How about this? - https://github.com/parallella/parallell ... sembly-opt