Documentation Errors

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Re: Documentation Errors

Postby ysapir » Tue Jul 02, 2013 9:58 pm

To add to @Hoernchen's answer - the IVT is indeed (physically) a part of the 1st SRAM bank. The way of setting the target addresses for the interrupt handlers is to write to the IVT entries, which are RAM. The IVT actually contains 10 entries (taking 40 bytes). The 64-bytes number in the table is just a round-up.

The only interrupt vector that really matters is the first one, at address 0x0000, since it is associated with the SYNC event, used to start the program (and even this can be (ab)used in some careful way). If you are extremely tight in space, you can theoretically use the other entries, provided that you don't use any other interrupts in your system.

A word is saved in the memory in 4 consecutive bytes, where the 1st byte's address is 32-bit aligned.
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Re: Documentation Errors

Postby Gravis » Tue Jul 02, 2013 10:38 pm

ysapir wrote:To add to @Hoernchen's answer - the IVT is indeed (physically) a part of the 1st SRAM bank.

so the IVT is really just polled before each operation?

ysapir wrote:The IVT actually contains 10 entries (taking 40 bytes). The 64-bytes number in the table is just a round-up.

is there any reason that the remaining bytes can't be used? seems like a waste to throw away space for six 32-bit operations.


arch ref version: 3.12.12.18 - section 6.1.2 wrote:"To accomplish this, the local memory is divided into four 8-byte-wide banks, each 8KB in size."

it may be clearer to say they are "64-bit-wide" instead since right below it refers to 64-bits. unless it's an error and they are 8-bit-wide.
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Re: Documentation Errors

Postby ysapir » Wed Jul 03, 2013 3:11 am

so the IVT is really just polled before each operation?


Why would you poll the IVT? The IVT vectors (possibly) contain the branch instructions to the respective ISR's. The vectors are used (not polled) when an interrupt event occurs.

is there any reason that the remaining bytes can't be used? seems like a waste to throw away space for six 32-bit operations.


What remaining? The extra 24 bytes? As I mentioned earlier, not only you can used these bytes, but if you are really that desperate, you could use the IVT entries as well.
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Re: Documentation Errors

Postby Gravis » Wed Jul 03, 2013 3:44 am

ysapir wrote:
so the IVT is really just polled before each operation?

Why would you poll the IVT? The IVT vectors (possibly) contain the branch instructions to the respective ISR's. The vectors are used (not polled) when an interrupt event occurs.

my bad, i confused the IVT with IRQ flags. i really should be getting more sleep. >_<;

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Re: Documentation Errors

Postby Gravis » Wed Jul 03, 2013 2:41 pm

.
Last edited by Gravis on Sat Jul 13, 2013 4:20 pm, edited 2 times in total.
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Re: Documentation Errors

Postby Gravis » Sat Jul 06, 2013 12:31 am

arch ref version: 3.12.12.18

Documentation Errors

---------------------------------------------------------------------------------------------

page 130) "Table 38: Epiphany Instruction Decode Table"
row 8, row 9 and row 10:
Rm2 Rm1 Rm0 Rn2 Rn1 Rn0 Rm2 Rm1 Rm0

should be
Rd2 Rd1 Rd0 Rn2 Rn1 Rn0 Rm2 Rm1 Rm0

---------------------------------------------------------------------------------------------

page 78) (ADD instruction)
<SIMM3 | SIM11> Three or eleven bit signed immediate value.

should be
<SIMM3 | SIMM11> Three or eleven bit signed immediate value.

---------------------------------------------------------------------------------------------


page 78) ADD instruction
page 119) SUB instruction

{ OV=1 }
else { OV=0 }

should be
{ AV=1 }
else { AV=0 }
Last edited by Gravis on Sun Jul 14, 2013 7:38 am, edited 2 times in total.
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Re: Documentation Errors

Postby Gravis » Sat Jul 13, 2013 4:02 pm

arch ref version: 3.12.12.18

Documentation Errors

---------------------------------------------------------------------------------------------

page 130) "Table 38: Epiphany Instruction Decode Table"
row 5 is labeled as
LDR/STR (PM-IMM) (16)

should be
LDR/STR (PM) (16)


---------------------------------------------------------------------------------------------

page 130) "Table 38: Epiphany Instruction Decode Table"
row 6 is labeled as

LDR/STR (DISP) (16)

should be
LDR/STR (DISP) (32)
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Re: Documentation Errors

Postby Gravis » Sun Jul 14, 2013 7:19 am

arch ref version: 3.12.12.18

Documentation Errors

---------------------------------------------------------------------------------------------
same error on many pages.

page 86) FABS instruction
page 88) FIX instruction
page 89) FLOAT instruction
page 90) FMADD instruction
page 91) FMUL instruction
page 92) FMSUB instruction
page 97) IMADD instruction
page 98) IMSUB instruction
page 99) IMUL instruction

N = RD[31]

should be
BN = RD[31]


---------------------------------------------------------------------------------------------

some instructions list flags in "Flags Updated:" that are not mentioned in the "Operation:" section

page 96) IADD instruction - flag BVS
page 97) IMADD instruction - flags BV, BIS
page 98) IMSUB instruction - flag BV
page 99) IMUL instruction - flag BV
page 100) ISUB instruction - flags BV, BIS, BUS, BVS

---------------------------------------------------------------------------------------------

some instructions mention flags in the "Operation:" section that are not listed in "Flags Updated:"

page 78) ADD instruction - flag AVS
page 119) SUB instruction - flag AVS
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Re: Documentation Errors

Postby Gravis » Sun Jul 14, 2013 11:43 am

arch ref version: 3.12.12.18

Documentation Errors

---------------------------------------------------------------------------------------------

page 119) SUB instruction
if ((RD[31] & ~RM[31] & RN[31]) | (RD[31] & ~RM[31] & RN[31]) )

should be
if ((RD[31] & ~RM[31] & RN[31]) | (~RD[31] & RM[31] & ~RN[31]) )
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Re: Documentation Errors

Postby Gravis » Sun Jul 14, 2013 6:48 pm

arch ref version: 3.12.12.18

Documentation Error

---------------------------------------------------------------------------------------------

page 87) FADD instruction
if (UnbiasedExponent(RD) > 127) {B OV=1 } else { BV=0}

should be
if (UnbiasedExponent(RD) > 127) { BV=1 } else { BV=0}
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