by Urhixidur » Thu Feb 26, 2015 5:13 pm
This thread would be a lot more maintainable if it were split into separate threads for each document (e.g. Epiphany Architecture Reference in one, Epiphany SDK Reference in another, etc.) and if each document thread were split into separate threads for each revision.
This said, my post concerns the Epiphany Architecture Reference, rev 14.03.11, page 136. Table 38 is a copy of table 37 on the preceding page, whereas it was meant to describe the DMAxAUTO1 Register (which holds the upper 32-bits of the DMA slave mode receiver register pair).
Epiphany Architecture Reference, rev 14.03.11, page 136. Table 39, bit [1] reads:
"Sets up DMA channel to work in master made"
but should read:
"Sets up DMA channel to work in master mode"
Epiphany Architecture Reference, rev 14.03.11, page 138, DMAxCOUNT reads:
"The upper 16 bits specify the outer loop of the DMA transfer and the and lower 16 bits of the register specify the number of inner loops."
but should read:
"The upper 16 bits specify the outer loop of the DMA transfer and the lower 16 bits of the register specify the number of inner loops."
Epiphany Architecture Reference, rev 14.03.11, page 139, DMAxSRCADDR reads:
"The updated address is equal to the old source address added with the value in the destination field in the stride register."
but should read:
"The updated address is equal to the old source address added with the value in the source field of the stride register."
DMAxDSTADDR should also change "field in the stride register" into "field of the stride register".
Epiphany Architecture Reference, rev 14.03.11, page 140, DMAxSTATUS, bit [3:0] reads:
"while the DMA is not in in an IDLE state"
but should be:
"while the DMA is not in an IDLE state"
Epiphany Architecture Reference, rev 14.03.11, page 141, DEBUGCMD reads:
"A write only alias register used to place control the debug state of the Epiphany core from an external agent."
but should be:
"A write-only alias register used to control the debug state of the Epiphany core from an external agent."
Epiphany Architecture Reference, rev 14.03.11, page 144, Table 51 (IMASK register) bits [9:0] reads:
"ILAT Latched interrupts waiting to enter CPU"
which is identical to the bits [9:0] line of Table 48 (ILAT register), page 142. I strongly suspect that Table 51 is incorrect, at least in its labelling.
Epiphany Architecture Reference, rev 14.03.11, page 147, page 58 (MEMSTATUS) reads:
"WRITE_BREACH Read from external agent attempted with DIS_EXT_WR==1"
but should be:
"WRITE_BREACH Write from external agent attempted with DIS_EXT_WR==1"
or maybe:
"WRITE_BREACH Read from external agent attempted with (DIS_EXT_WR_MMR || DIS_EXT_WR_MEM)==1"
because there is no DIS_EXT_WR bit.
In the same table, we read:
"XWRITE_BREACH Write to on-chip cores attempted with DIS_CORE_XWR=1"
which should be:
"XWRITE_BREACH Write to off-chip attempted by a core with DIS_CORE_XWR=1"
I also presume that if a core has write-protected its local memory with MEMPROTECT's PAGE0 through PAGE7 bits, another core's attempt to write there would cause a MEMSTATUS MEM_FAULT of the target core? What is the exception raised on the writing core in this scenario?
