existing 16core chips
Posted: Sat Sep 30, 2017 10:05 am
so one problem, it seems, is although the architecture is scalable, it's difficult to scale software -
e.g. if you write and tune something for a 16 core 512k chip , the decisions might be quite different compared to the 1024core, 64mb chip, where you can fit a much more interesting problem directly in the scratchpads; and similarly, although there are clusters out there, they use message passing / networks, whereas the epiphany uses PGAS.
Would the world be interested in using some of the remaining parallela chips to build a grid, made available online for testing and tuning code much more similar in shape to what the Epiphany-5 could handle. (e.g. imagine if there was a 32x16 x 16core,64mb grid sat online with some web interface)
.. I guess that would still mean designing and building an entirely new board, so maybe this is just as much of a pipedream as even getting the 1024 core chip.. and if you could get any funding together you might as well dive in with that
e.g. if you write and tune something for a 16 core 512k chip , the decisions might be quite different compared to the 1024core, 64mb chip, where you can fit a much more interesting problem directly in the scratchpads; and similarly, although there are clusters out there, they use message passing / networks, whereas the epiphany uses PGAS.
Would the world be interested in using some of the remaining parallela chips to build a grid, made available online for testing and tuning code much more similar in shape to what the Epiphany-5 could handle. (e.g. imagine if there was a 32x16 x 16core,64mb grid sat online with some web interface)
.. I guess that would still mean designing and building an entirely new board, so maybe this is just as much of a pipedream as even getting the 1024 core chip.. and if you could get any funding together you might as well dive in with that