1024-core Epiphany-V news

[jar]

The story is now out about the 16nm, 1024-core, 64 MB double-precision floating point processor. I'll update the list below as more news is added. Keep at eye on http://www.adapteva.com and http://www.parallella.org for other details. Feel free to discuss and ask questions.

Blog announcement: https://www.parallella.org/2016/10/05/e ... processor/
Hardware details: https://www.parallella.org/wp-content/u ... re_soc.pdf

Other news:
http://www.pcworld.com/article/3127176/ ... allop.html
http://www.eetimes.com/document.asp?doc_id=1330568
http://www.nextplatform.com/2016/10/13/ ... piphany-v/ (best article yet, IMO)

[Melkhior]

[nickoppen]

64MB of on board memoy divided by 1024 cores make 512KB per core? Am I right or is it a little more complicated?

Very excited btw.

[polas]

[jar]

I just added the EETimes article which is a better than the PCWorld article, IMHO.

Just to clear up some details...there is 64 KB (65,536 bytes) per core, which is twice what the per-core memory in Parallella. With 1024 cores, that's 64 MB (67,108,864 bytes). Consider that the beefiest 22-core Intel Xeon E5-2699 v4 has 55 MB of L3 cache. Yes, most of E5 is SRAM. There is no "cache" or "cache coherency". It's still a user managed scratchpad like E3/E4.

Some of you may be confused about the "1 MB per core". That is the memory map per core, but anything beyond the 64KB and registers is irrelevant. You can think of it like a book with 1024 pages and an index to each one of them. But only the first 64 pages can be used or have any content. It's really meant to maintain binary compatibility for the future if someone decides to add up to 1 MB per core. This concept was also in E3/E4, but you may not have known.

[Melkhior]

[jar]

[Melkhior]

[polas]

[Melkhior]