I couldn't commit to an LLVM port per se, but if I get time I would like to play with some similar JIT-type stuff across multiple processors, with (implicit) clock-level synchronization, using the excellent cycle-level comms model already presented in the docs (with its curious 1/2 cycles!) Just for fun, you understand
And I want this stuff partly just because the nerd in me needs to see it, because it gives him power over the hardware (even if he never uses that power).