new chinese supercomputer, many-core?

[dobkeratops]

if this hasn't been posted yet,

http://www.extremetech.com/extreme/2304 ... taihulight

seems to be in the same space, a many-core chip..

" The TOP500 report said that the chip also lacks any traditional L1-L2-L3 cache, and instead has 12KB of instruction cache and 64KB “local scratchpad” that works sort of like an L1 cache."

sounds rather Epiphany-esque.

If that's a 12kb instruction *cache* along side the scratchpad, that's a rather interesting mix - an I-Cache doesn't suffer from coherency issues, if it's read only; that might make it a little easier to program (but would they need an efficient way of loading instructions into multiple cores without going to main memory for each, maybe they could check their neighbours or something, or maybe you'd still need to issue some instruction pre-fetch hint for common code).

Or is it just harvard architecture scratchpads?