india/RISC-V/neuromorphic processor

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india/RISC-V/neuromorphic processor

Postby dobkeratops » Fri Mar 25, 2016 7:46 pm

http://www.eetimes.com/document.asp?_mc ... e_number=2

According to this along with RISC-V india is developing some sort of neuromorphic accelerator, interestingly the block diagram uses the acronym 'SPU' (reminding me of CELL) for elements with local memories connected together, but I'm guessing it's more akin to IBM TrueNorth.

Given how much of what true north does might be down to low precision , I wonder how close a processor (with scratchpads) could get, (e.g. especially if it had instructions like POPCOUNT).
I know CELL's instruction set was already tailored to video (and it had scratchpads + inter-scratchpad DMA): I would speculate there would be overlap between the kind of processing you need for video & image recognition (e.g. some video motion estimation algorithms use bit planes, and of course low precision arithmetic). I'm sure you could make such extensions to a RISC-V chip.

Could using traditional processor instructions to implement sparsity (run length encoding to skip zeros, or indexing into tables of weights etc) get the same results as these proposed spike engines, I wonder, whilst running on hardware that can run a wider range of tasks. I have difficulty imagining these spike engines being as good for robot control (then again, biological brains clearly manage)

(a RISC-V host combined with attached RISC-V accelerators would be rather nice... )
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Re: india/RISC-V/neuromorphic processor

Postby 8l » Sun Mar 27, 2016 12:10 am

yeah i read the article, too.
i wish riscv becoming more general platform, like amd/intel/etc.
i think agner's proposal + riscv is gr8.

Proposal for an ideal extensible instruction set
http://agner.org/optimize/blog/read.php?i=421
http://agner.org/optimize/blog/read.php?i=428&v=t
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