Parallella Community

Hi,

I was measuring performance of Parallella board in terms of TCP throughput and got results of ~600Mbps under best conditions (128K blocks, single stream). But according to Xilinx XAPP1082 reference design it is possible to gain up to 900Mbps.

What kind of optimizations do you think I can make to Linux kernel to raise the bar?
Is it possible to implement CSO offload easily in FPGA?

I posted the exact results and measurement settings in my blog .

Thanks!
Meir Tseitlin

Nice work!

AFAIK the 900Mbps number is only achievable for the PL ethernet port. Running on the 667MHz ARM, 600Mbps seems to be the limit. I don't think it's driver related. (although with an older driver we were limited to 300Mbps so it's possble...)