by piotr5 » Sat Sep 19, 2015 2:38 pm
in spirit parallella already is a som-design. it has fpga and thereby future versions can be programmed to cooperate with old carrier-boards. so instead of pleading for a som, create a carrier-board that can host 16 parallellas (maybe 8 on each side) and link the included epiphany chips into a chain -- if future versions of epiphany stay compatible with the current eLink protocol. the point is, fpga provides a connection among the boards, maybe faster than eLink. with smart carrier-board design you could boot up the parallellas in sequence at the right timing.for obtaining much higher transfer-frequencies than a single board could. this way the carrier module could become a som itself, flexible enough to communicate with future generations of motherboards...
also I must point at my threads in this requests-thread. they point out a weakness of epiphany-chips: they aren't scaleable. you can only have 4k epiphany-cores in total. to overcome such limitation I propose there a circuit for transforming the eLink protocol on the fly, before sending it to another board, thereby allowing for adding a 3rd eLink connector to the board. of course arm is not affected by this limitation, therefore what you propose here is doable without redesigning a board. unfortunately what I propose is beyond the usual som concept, I want each parallella to work as both, module and carrier-board for 2 other parallellas.
and finally, if someone really creates an epiphany powered som with the purpose of equipping supercomputers with them, afterall the hardware is open and we don't require help from adapteva for that, then it better be a board with some arm-cpu making use of the whole lot of 4k epiphany cores (or maybe 3840==16x15 epiphany and the arm-processor connected to the 1920 pins == 16x60 eLink pins for each of the 2 ends of that grid to form a loop) by communicating through 2-4 eLink connections (resp. 32 if you formed the loop) and pretending to be one of them. this cpu then could take over communication to the carrier board, the necessary bottle-neck so to say. how much energy does each epiphany chip consume? definitely less than 2w, that's less than 500w for 8k gigaflops. (each epiphany core can run at 1Ghz and calculate an mul-add at each tick, that's 2gflops per core.) if creation of a parallella board costs 100$, and fpga is consuming the most amount, I suppose a bulk-order of epiphany chips would cost less than 50$ the piece, that's <12800$ per 8teraflop module. I think xeon phi is more expensive, but intel's pcie-card has definitely more memory than the total of 128m available on the epiphany cores plus a maximum amount of 4g added to the 32bit arm -- not to forget the bottle-neck of 1-16m shared memory through which epiphany can fiddle data-transfers into and out of the 4g managed by arm or the module...
either way, you'd better be quick with such development, not sure how long intel will remain at its low gflops count per module. maybe by the time you developed all this, intel's offer would look much more attractive, considering the development-costs you'd have for hardware and software. in effect I suspect adapteva did look thoroughly into that route of action, calculated the risks and possible profits, and decided it isn't worth the hassle when compared to the educational path raspberry pi did choose...