A local intermediate FPGA memory ?

[theover]

I have followed most threads here I thought might interest me and I recall a mention of a communication example from Epiphany to FPGA or something.

I'm interested in writing to and reading from a FPGA memory block, preferably bi-directional from both the ARM core(s) (either direct or via DMA memory) and from the Epiphany.

I could imagine taking an Epiphany page number that doesn't exist, and making writes via the standard library calls (I didn't try the latest upgrade however) which end up in that "intermediate" FPGA memory block, which could in principle also act as a cache, or memory extension for the Epiphany, but that's not my primary purpose.

Has anything been made or set up yet for such an idea to work ?

Theo V.

[greytery]

Access to that FPGA memory from the Epiphany will be via the eLink. The in the FPGA currently maps memory access from the cores to the 32MB shared memory and would need to be recoded. Search for the threads on "shared memory" for discussion, including page addressing. However that is mainly about extending the amount of shared memory.

Since the eLink interface is the throttle here, I'm not sure that you get much of a benefit on using FPGA memory vs the shared memory - some, but is it enough?? If the data content is shared only between FPGA logic and cores then it could be faster, but I guess not if shared between ARM and cores.

Some work was done on a was posted on Github by Andreas but AFAIK is not complete. This may be (similar to) the sort of thing what you are looking for...

HTH

[theover]

Alright today I didn't take time to look up more threads, and I found the link to Andreas' mailbox code, which should be a good starting point but I saw only the one file it pointed to, not the whole project.I don't know if it's easy to spilce the example in with the main FPGA code. I Did look up the various Verilog parts (I suppose many savvy hardware designers with no theoretical tainting prefer the history of Verilog over VHDL, that's a remaining piece of knowledge that seems to come from my short 90s experience with the subjects) which make up the FPGA interfaces to the AXI bus, the Epiphany, and the sort of word with adapter in between, and I can compile the version 1 code and make modifications to the FPGA which work in practice, so I am interested, but not all too keen on spending the amount of time I would need to get the whole idea working, especially with on top of the language skill requirement (I have to rethink designing hardware, which I'm good at, into the HDL, which I'm hardly fluent at) the fact that certain constructs get interpreted and according to Andreas' log there are compiler issues.

I'll look at the rest of the example and do some searching. A at least order of magnitude 100MB/s construction with a FPGA based dedicated shared memory between the ARM and the Epiphany cores that works reliable and is well enough accessible from ARM and Epi. cores would sure mean a lot.

T.

[dobkeratops]