creating a output register/interrup from PL to arm processor

[dipin]

hi,

finally i successfully implemented https://www.parallella.org/2016/01/21/creating-an-fpga-accelerator-in-15-minutes/ this project and added a counter. now output of the adder is printing in the Ubuntu terminal. Here i need an extra control signal or register to give some control to the total design. when the counter reaches a particular value, i need to give a signal to arm processor. so anybody know how to how to add and extra output reg to above design ?
any help is really appreciated
thanks and regards
dipin divakar

[dipin]

hi,
what i am trying to do is an interrupt which will goes from fpga to arm processor.. if anybody had any clue please help...
i can give it to the zynq processor by enabling the interrupt option. but how can i acess it in the arm processor
thanks in advance

[olajep]

hi,
what i am trying to do is an interrupt which will goes from fpga to arm processor.. if anybody had any clue please help...
i can give it to the zynq processor by enabling the interrupt option. but how can i acess it in the arm processor
thanks in advance

Check out the oh elink mailbox implementation:

Some pointers:

parallella_base verilog top block
https://github.com/parallella/oh/blob/m ... lla_base.v (search for mailbox_irq)

Vivado 'top block'
https://github.com/parallella/oh/blob/m ... d.tcl#L248 (search for mailbox_irq)

Device tree:
https://github.com/parallella/parallell ... 2677-L2678

Driver:
https://github.com/parallella/parallell ... 1.dtsi#L94

HTH
// Ola

[dipin]

HI,

thanks for the replay olajep
i connected the my interrupt to zynq processor IRQ_F2P pin. and i am using this c program https://github.com/Xilinx/embeddedsw/blob/master/XilinxProcessorIPLib/drivers/scugic/examples/xscugic_example.c to get the interrupt working. but my problem is the xil_drivers .my drivers are throwing error .

now how can i get the interrupt in arm side of the parallella board . which drivers are required for it. Is it xilinx drivers or we need to write our on ??
did parallella will supply some interface for this?

please share your views
thanks and regards

[olajep]

HI,

thanks for the replay olajep
i connected the my interrupt to zynq processor IRQ_F2P pin. and i am using this c program https://github.com/Xilinx/embeddedsw/blob/master/XilinxProcessorIPLib/drivers/scugic/examples/xscugic_example.c to get the interrupt working. but my problem is the xil_drivers .my drivers are throwing error .

IRQ_F2P is a 16 bit wide bus so you have to decide which pin you map it to.

See this xilinx forums thread:
https://forums.xilinx.com/t5/Embedded-L ... d-p/275370

now how can i get the interrupt in arm side of the parallella board . which drivers are required for it. Is it xilinx drivers or we need to write our on ??
did parallella will supply some interface for this?
please share your views
thanks and regards

if you modify the device tree you should be able to use the uio_pdrv_genirq driver and then access your PL from user space.
This has been discussed previously on this forum search for "UIO"

// Ola

[dipin]

Hi @olajep ,

if you modify the device tree you should be able to use the uio_pdrv_genirq driver and then access your PL from user space.
This has been discussed previously on this forum search for "UIO"

How can i do that ?

One more thing is is it good to do either using "elink mailbox example " or using "UIO driver" which is a better idea ?
I tried using uio, I recompiled the kernel, but still its not working (uio drivers not showing up )

Thanks and Regards

[cpantel]

hi dipin

Have you shared your experience somewhere? I am stuck with some common errors

hi,

finally i successfully implemented https://www.parallella.org/2016/01/21/creating-an-fpga-accelerator-in-15-minutes/ this project and added a counter. now output of the adder is printing in the Ubuntu terminal. Here i need an extra control signal or register to give some control to the total design. when the counter reaches a particular value, i need to give a signal to arm processor. so anybody know how to how to add and extra output reg to above design ?
any help is really appreciated
thanks and regards
dipin divakar

[dipin]

HI,
If you tell me what is the problem you are finding, i can help you
hints:: you have to use the old version of vivado.. 15.2 or 15.4 i think...
else the ip will show as a black box (because it will be empty if you uses the script).
if you are using 15.4, again you have to change the script file to 15.4 from 15.2.
then in the program, you have to change to "dev/epiphany" to "dev/mem"
then only it will map to fpga memory.

thanks and regards

[cpantel]

Hi dipin

please look this thread:

viewtopic.php?f=49&t=3411

I have used both 15.2 and 15.4

Thank you

[dipin]

Hi,

now what was the problem you are facing, same as in the post you mentioned .

thanks