Page 1 of 2

Cannot boot after adding FPGA accelerator

PostPosted: Sun May 21, 2017 9:14 am
by jimmystone
Hi, All

I cannot boot my Parallella after I add my FPGA accelerator to the headless_e16_z7020 project
I am sure I can make my Parallella without this accelerator adding to my headless_e16_z7020 project when replacing parallella.bit.bin
The UART is printing this message again and again. I think the Parallella found something wrong and reboot.
Is there any special setting if I want to add some logic in the Zynq part?
Can anyone help? Thanks
Code: Select all
                                                                               
U-Boot 2012.10-00003-g792c31c (Jan 03 2014 - 12:24:08)                         
Hit any key to stop autoboot:  0                                               
Configuring PL and Booting Linux...                                             
Device: SDHCI                                                                   
Manufacturer ID: 3                                                             
OEM: 5344                                                                       
Name: SU04G                                                                     
Tran Speed: 50000000                                                           
Rd Block Len: 512                                                               
SD version 2.0                                                                 
High Capacity: Yes                                                             
Capacity: 3.7 GiB                                                               
Bus Width: 4-bit                                                               
reading parallella.bit.bin                                                     
                                                                               
4045568 bytes read

Re: Cannot boot after adding FPGA accelerator

PostPosted: Mon May 22, 2017 7:29 am
by miguel_rodrigues
If you simply replaced the provided FPGA bitstream with your own that doesn't implement the glue logic required for ARM <-> Epiphany communication, I believe that the error is expected. Or maybe it has to do with memory zones.

What were the exact steps you followed to add your accelerator after opening the Parallella Vivado project?

Re: Cannot boot after adding FPGA accelerator

PostPosted: Mon May 22, 2017 2:45 pm
by jimmystone
miguel_rodrigues wrote:If you simply replaced the provided FPGA bitstream with your own that doesn't implement the glue logic required for ARM <-> Epiphany communication, I believe that the error is expected. Or maybe it has to do with memory zones.

What were the exact steps you followed to add your accelerator after opening the Parallella Vivado project?


I keep all the original logic in Parallella project. and Add an my accelerator as an IP to this project in the system.bd.
This IP use a new clock FCLK_CLK1, and connect ARM with UART0.
reset pin is connect like this: FCLK_RESET1_N ------ proc_sys_reset_1 ----- my IP rst pin
Then I save the system.bd file and wrote it to tcl with
Code: Select all
write_bd_tcl -force system_bd.tcl

then ./build.sh again

BTW, I have test UART0 working correctly with its RX connect to TX in a loop test, device tree is updated, and FPGA/Linux seems work all right.
What I missing?
Thanks.

Re: Cannot boot after adding FPGA accelerator

PostPosted: Tue May 23, 2017 7:23 am
by sebraa
Does your accelerator work if you replace the FPGA bitstream at runtime (dd if=bitstream.bit.bin of=/dev/xdevcfg)?
You need the Xilinx driver for doing so, so if you don't have it, you may need to build your own kernel.

Re: Cannot boot after adding FPGA accelerator

PostPosted: Wed May 31, 2017 12:31 pm
by jimmystone
sebraa wrote:Does your accelerator work if you replace the FPGA bitstream at runtime (dd if=bitstream.bit.bin of=/dev/xdevcfg)?
You need the Xilinx driver for doing so, so if you don't have it, you may need to build your own kernel.


I finally found out this maybe the root cause:
1. My accelerator works at 50MHz using FCLK1. (about 50MHz, there is timming issue for PL setup timing)
2. It seems FCLK1 is 200MHz when Linux booted
3. I try to simplify my accelerator, and it can boot to Linux, and I changed FCLK1 to 50MHz, it works fine.
I read the thread as reference https://parallella.org/forums/viewtopic.php?f=51&t=3443

My question now comes to
I think it is the timming issue in FPGA logic cause the ZYNQ boot fail.
Is there any way to configure FCLK1 before it loads the FPGA login into PL?

Thanks.

Re: Cannot boot after adding FPGA accelerator

PostPosted: Wed May 31, 2017 5:03 pm
by sebraa
I always boot with the original Epiphany bitstream, and then replace the FPGA logic at runtime (writing it to /dev/xdevcfg). This way, I can check (or unload) the Epiphany driver before loading my accelerator, which avoids a crash (my bitstreams do not contain the eLink interface, so the Epiphany driver must not be loaded).

Loading at runtime seems to reconfigure the FCLK clock speed, although I haven't tested this to be sure.

Re: Cannot boot after adding FPGA accelerator

PostPosted: Thu Jun 01, 2017 7:29 am
by miguel_rodrigues
I do also boot with the original bitstream and replace with my own at runtime. However, simply loading the bitstream won't change your FCLKs, you need to do it explicitly before replacing the bitstream with your own (like the thread you reference mentions).

To achieve what you want, I would also ask over at Xilinx forums as this is not a question specific to Parallella.

But if I were you, I would simply write a script that executed as soon as Linux finishes booting and replaces the original bitstream with your own and changes clocks accordingly. From what I gather, you would obtain equivalent functionality :)

Re: Cannot boot after adding FPGA accelerator

PostPosted: Sun Jun 04, 2017 4:26 am
by jimmystone
Hi, All

Update status
I try to change the fclk3 freq to 50MHz with shell script
https://gist.github.com/Kirill888/24385a36697959924d78

Then I try to update PL at runtime with this cmd
Code: Select all
parallella@parallella:~$ sudo dd if=myacc.fclk3_50MHz.uart0.bit.bin of=/dev/xdevcfg

The whole system seems reboot again

But if I try to configure the original PL img at runtime, with this cmd
Code: Select all
parallella@parallella:~$ sudo dd if=parallella.bit.bin of=/dev/xdevcfg
7901+1 records in
7901+1 records out
4045568 bytes (4.0 MB) copied, 0.534912 s, 7.6 MB/s

It seems fine.

Any idea?

Re: Cannot boot after adding FPGA accelerator

PostPosted: Wed Jun 07, 2017 3:48 pm
by jimmystone
Hi, All

Update!
I can make my accelerator work at fclk3=35MHz, If I setting fclk3 above this freq, system will reboot.
I think there maybe power issue on Parallella.

Is there any way make a better power for Parallella?
Thanks.

Re: Cannot boot after adding FPGA accelerator

PostPosted: Tue Jun 20, 2017 3:40 pm
by olajep
jimmystone wrote:Hi, All

Update status
I try to change the fclk3 freq to 50MHz with shell script
https://gist.github.com/Kirill888/24385a36697959924d78

Then I try to update PL at runtime with this cmd
Code: Select all
parallella@parallella:~$ sudo dd if=myacc.fclk3_50MHz.uart0.bit.bin of=/dev/xdevcfg

The whole system seems reboot again

Weird. I'd expect the board to freeze if something was wrong with the new bitstream, not reboot.
What Parabuntu release are you using (2016.11 or 2016.3) ?
jimmystone wrote:But if I try to configure the original PL img at runtime, with this cmd
Code: Select all
parallella@parallella:~$ sudo dd if=parallella.bit.bin of=/dev/xdevcfg
7901+1 records in
7901+1 records out
4045568 bytes (4.0 MB) copied, 0.534912 s, 7.6 MB/s

It seems fine.

Any idea?

Try removing the epiphany module before reconfiguring the FPGA
Code: Select all
$ sudo rmmod epiphany
$ sudo dd if=myacc.fclk3_50MHz.uart0.bit.bin of=/dev/xdevcfg


// Ola