Timing violation of Parallella PFGA project
Posted: Sun May 21, 2017 8:58 amHi, All
I am using the Oh! to compile a new FPGA of
headless_e16_z7020
And I notice there are some timing violation after PAR in Vivado.
Do these violations matter? Should I mask these path with false path?
Thanks.
I am using the Oh! to compile a new FPGA of
headless_e16_z7020
And I notice there are some timing violation after PAR in Vivado.
Do these violations matter? Should I mask these path with false path?
Thanks.