As mentioned in the the "minimal setup" thread here, indeed there appears to be a free C based IP design module in the latest Vivado download.
I haven't tried it yet but read through the main documentation which looks promising.
In principle, you can turn a function (and it's sub-functions) in a C program into a FPGA design, and most of it automatically, and there are HDL libraries for various C functions (including math, but I don't know how much of it, video processing, etc). Vivado will create state machines, and even Zynq interfaces automatically for your C program turned HDL. Arrays turn into block memories, and there optimization and source code block functions.
A "minimal" approach with this addition will be very useful, I suppose.
Theo V.