Parallella_7010_headless

[ianguzv]

Hi Everyone,

I have a parallella board (SKU p1601-01) based on the Zynq 7010 and I'm trying to start configuring my own designs in the FPGA.

At first i didn't know what kind of Zynq i was working with, so i started following this tutorial (based on the 7020 project) https://www.parallella.org/2015/03/23/n ... in-vivado/ and generated the final bitstream to program the FPGA but when i copied that bitstream to the SD card it didn't work, that's when i realized that i had a 7010.

Since the parallella project 7010 is older than the 7020, i'm trying now to use PlanAhead to generate the bitstream, so i started following this tutorial http://parallellagram.org/parallella-fp ... oject-repo.

But when i added all the hdl sources and tried to synthetize the project i got the following errors :

[Project 1-19] Could not find the file /home/ian/Downloads/parallella-hw-master/fpga/old/hdl/elink/ewrapper_link_txo.v.
[Project 1-19] Could not find the file /home/ian/Downloads/parallella-hw-master/fpga/old/hdl/elink/ewrapper_link_rxi.v.
[Project 1-19] Could not find the file /home/ian/Downloads/parallella-hw-master/fpga/old/hdl/common/mux4.v.
[Project 1-19] Could not find the file /home/ian/Downloads/parallella-hw-master/fpga/old/hdl/axi/axi_slave_addrch.v.
[Project 1-19] Could not find the file /home/ian/Downloads/parallella-hw-master/fpga/old/hdl/elink/ewrapper_link_transmitter.v.
[Project 1-19] Could not find the file /home/ian/Downloads/parallella-hw-master/fpga/old/hdl/elink/ewrapper_link_receiver.v.
[Project 1-19] Could not find the file /home/ian/Downloads/parallella-hw-master/fpga/old/hdl/elink/ewrapper_io_tx_slow.v.
[Project 1-19] Could not find the file /home/ian/Downloads/parallella-hw-master/fpga/old/hdl/elink/ewrapper_io_rx_slow.v.
[Project 1-19] Could not find the file /home/ian/Downloads/parallella-hw-master/fpga/old/hdl/clocks/io_clock_gen_600mhz.v.
master/fpga/boards/parallella-I/constraints/parallella_z7020_loc.ucf.
[Project 1-19] Could not find the file /home/ian/Downloads/parallella-hw-master/fpga/boards/parallella-I/constraints/parallella_z70x0_loc.ucf.


However, i managed to solve this problem, but then when i tried to synthetize the project these errors showed up :


[HDLCompiler 711] Found more than one declaration of port <emaxi_rid>. ["/home/ian/Downloads/parallella-fpga-tutorials-master/Tutorial000_BaseProject/Project_7010/Project_7010.srcs/sources_1/imports/parallella-I/parallella.v":106]
[HDLCompiler 711] Found more than one declaration of port <emaxi_rdata>. ["/home/ian/Downloads/parallella-fpga-tutorials-master/Tutorial000_BaseProject/Project_7010/Project_7010.srcs/sources_1/imports/parallella-I/parallella.v":107]
[HDLCompiler 711] Found more than one declaration of port <emaxi_rresp>. ["/home/ian/Downloads/parallella-fpga-tutorials-master/Tutorial000_BaseProject/Project_7010/Project_7010.srcs/sources_1/imports/parallella-I/parallella.v":108]
[HDLCompiler 711] Found more than one declaration of port <emaxi_rlast>. ["/home/ian/Downloads/parallella-fpga-tutorials-master/Tutorial000_BaseProject/Project_7010/Project_7010.srcs/sources_1/imports/parallella-I/parallella.v":109]
[HDLCompiler 711] Found more than one declaration of port <emaxi_rvalid>. ["/home/ian/Downloads/parallella-fpga-tutorials-master/Tutorial000_BaseProject/Project_7010/Project_7010.srcs/sources_1/imports/parallella-I/parallella.v":110]
[HDLCompiler 711] Found more than one declaration of port <emaxi_rid>. ["/home/ian/Downloads/parallella-fpga-tutorials-master/Tutorial000_BaseProject/Project_7010/Project_7010.srcs/sources_1/imports/parallella-I/parallella.v":111]
[HDLCompiler 711] Found more than one declaration of port <emaxi_rdata>. ["/home/ian/Downloads/parallella-fpga-tutorials-master/Tutorial000_BaseProject/Project_7010/Project_7010.srcs/sources_1/imports/parallella-I/parallella.v":112]
[HDLCompiler 711] Found more than one declaration of port <emaxi_rresp>. ["/home/ian/Downloads/parallella-fpga-tutorials-master/Tutorial000_BaseProject/Project_7010/Project_7010.srcs/sources_1/imports/parallella-I/parallella.v":113]
[HDLCompiler 711] Found more than one declaration of port <emaxi_rlast>. ["/home/ian/Downloads/parallella-fpga-tutorials-master/Tutorial000_BaseProject/Project_7010/Project_7010.srcs/sources_1/imports/parallella-I/parallella.v":114]
[HDLCompiler 711] Found more than one declaration of port <emaxi_rvalid>. ["/home/ian/Downloads/parallella-fpga-tutorials-master/Tutorial000_BaseProject/Project_7010/Project_7010.srcs/sources_1/imports/parallella-I/parallella.v":115]
[HDLCompiler 711] Found more than one declaration of port <emaxi_rid>. ["/home/ian/Downloads/parallella-fpga-tutorials-master/Tutorial000_BaseProject/Project_7010/Project_7010.srcs/sources_1/imports/parallella-I/parallella.v":116]
[HDLCompiler 711] Found more than one declaration of port <emaxi_rdata>. ["/home/ian/Downloads/parallella-fpga-tutorials-master/Tutorial000_BaseProject/Project_7010/Project_7010.srcs/sources_1/imports/parallella-I/parallella.v":117]
[HDLCompiler 711] Found more than one declaration of port <emaxi_rresp>. ["/home/ian/Downloads/parallella-fpga-tutorials-master/Tutorial000_BaseProject/Project_7010/Project_7010.srcs/sources_1/imports/parallella-I/parallella.v":118]
[HDLCompiler 711] Found more than one declaration of port <emaxi_rlast>. ["/home/ian/Downloads/parallella-fpga-tutorials-master/Tutorial000_BaseProject/Project_7010/Project_7010.srcs/sources_1/imports/parallella-I/parallella.v":119]
[HDLCompiler 711] Found more than one declaration of port <emaxi_rvalid>. ["/home/ian/Downloads/parallella-fpga-tutorials-master/Tutorial000_BaseProject/Project_7010/Project_7010.srcs/sources_1/imports/parallella-I/parallella.v":120]
[HDLCompiler 711] Found more than one declaration of port <emaxi_rid>. ["/home/ian/Downloads/parallella-fpga-tutorials-master/Tutorial000_BaseProject/Project_7010/Project_7010.srcs/sources_1/imports/parallella-I/parallella.v":168]
[HDLCompiler 711] Found more than one declaration of port <emaxi_rdata>. ["/home/ian/Downloads/parallella-fpga-tutorials-master/Tutorial000_BaseProject/Project_7010/Project_7010.srcs/sources_1/imports/parallella-I/parallella.v":169]
[HDLCompiler 711] Found more than one declaration of port <emaxi_rresp>. ["/home/ian/Downloads/parallella-fpga-tutorials-master/Tutorial000_BaseProject/Project_7010/Project_7010.srcs/sources_1/imports/parallella-I/parallella.v":170]

Right now, i'm stuck here and i'm trying to solve this problem ........

Any comment , feedback or suggestion would be very very apreaciated !

Best Regards,

Ian

[peteasa]

http://parallellagram.org/cat/Parallell ... 0Tutorials are good to follow. They worked for me with the old elink and the old kernel v3.14. I am now progressing on to use the new elink and kernel v3.19.

Olde parallella-hw that I was using was SHA1 ID ce97134bc01e8f3b8374e0e74b2ca191c8873f59 "Step #3 clarification" .. it worked just fine with PlanAhead as per the tutorial with matching ubuntu dated 9/11/14..

I also used the new elink as per https://www.parallella.org/2015/03/23/n ... in-vivado/ with kernel v3.14 but that was from parallella-linux SHA1 ID 40a90c3002460adabeb1213da554ffbe66e21391 ie a version with the necessary changes to the epiphany.c character driver for the new link.

Key it to get matching kernel and fpga to get the elink to work.

[ianguzv]

Thanks for your helpful reply peteasa,

I tried with the ce97134bc01e8f3b8374e0e74b2ca191c8873f59 and it compiled but when I generated the raw bitstream it didn't work in the FPGA. However, I suspect it is the kernel problem. I check my router configuration and I am actually getting an IP address for the Parallella board, which makes me think that the problem is OS related.

I think i'm gonna try changing the kernel to v3.14. But I have not been able to find it so far.

Do you know where can I download the v3.14 kernel image?

[josemonsalve2]

Peteasa, Thanks for your help!

It would be nice if you tell us when you figure how to compile the bitstream for the 3.19.

Hi Ian,

The old images can be found here:

[peteasa]