Splicing messages over the Epiphany FPGA connection
Posted: Fri Feb 13, 2015 9:30 pmHi
For a while now I've have the idea of using the existing AXI interface in the FPGA from the ARM cores to the Epiphany processor to carry some messages of my own from and to the FPGA.
Maybe someone has done this already, or someone can give a good indication of address ranges involved (admittedly it's been a while since I've felt slightly motivated to work on this) and what a good point of message intercept and inject could be in the protocol implementation of the Adapteva FPGA code, like before or after packaging and size conversion, and if there are good sync signals to be found.
I don't have the intention to add a few percents of speed here and there, but a side effect of the method could be to besides allowing smooth and fast enough ARM<->FPGA communication (instigated from either end, I don't care) that certain adddress range messages to the Epiphany could have their payload directly filled in from FPGA memory elements, and maybe FPGA register files could be directly accessed from the Epiphany (without interference from the AXI latencies and processor interrupt response time)!
Theo V.
For a while now I've have the idea of using the existing AXI interface in the FPGA from the ARM cores to the Epiphany processor to carry some messages of my own from and to the FPGA.
Maybe someone has done this already, or someone can give a good indication of address ranges involved (admittedly it's been a while since I've felt slightly motivated to work on this) and what a good point of message intercept and inject could be in the protocol implementation of the Adapteva FPGA code, like before or after packaging and size conversion, and if there are good sync signals to be found.
I don't have the intention to add a few percents of speed here and there, but a side effect of the method could be to besides allowing smooth and fast enough ARM<->FPGA communication (instigated from either end, I don't care) that certain adddress range messages to the Epiphany could have their payload directly filled in from FPGA memory elements, and maybe FPGA register files could be directly accessed from the Epiphany (without interference from the AXI latencies and processor interrupt response time)!
Theo V.