Parallella FPGA Tutorials available

Using Zynq Programmable Logic and Xilinx tools to create custom board configurations

Re: Parallella FPGA Tutorials available

Postby steddyman » Mon Jan 05, 2015 6:06 pm

Now I have everything working, without making any changes I am trying to synthesize the 7020 HDMI project.

It is returning the following errors for me:

[HDLCompiler 267] Cannot find port processing_system7_0_I2C0_SDA_pin on this module ["D:/p/parallella-hw/fpga/projects/parallella_7020_hdmi/parallella_7020_hdmi.srcs/sources_1/imports/parallella_7020_hdmi/system_stub.v":266]
[HDLCompiler 267] Cannot find port processing_system7_0_I2C0_SCL_pin on this module ["D:/p/parallella-hw/fpga/projects/parallella_7020_hdmi/parallella_7020_hdmi.srcs/sources_1/imports/parallella_7020_hdmi/system_stub.v":267]
[HDLCompiler 267] Cannot find port processing_system7_0_GPIO_I_pin on this module ["D:/p/parallella-hw/fpga/projects/parallella_7020_hdmi/parallella_7020_hdmi.srcs/sources_1/imports/parallella_7020_hdmi/system_stub.v":351]
[HDLCompiler 267] Cannot find port processing_system7_0_GPIO_O_pin on this module ["D:/p/parallella-hw/fpga/projects/parallella_7020_hdmi/parallella_7020_hdmi.srcs/sources_1/imports/parallella_7020_hdmi/system_stub.v":352]
[HDLCompiler 267] Cannot find port processing_system7_0_GPIO_T_pin on this module ["D:/p/parallella-hw/fpga/projects/parallella_7020_hdmi/parallella_7020_hdmi.srcs/sources_1/imports/parallella_7020_hdmi/system_stub.v":353]


Shouldn't the project just compile?

Thanks
steddyman
 
Posts: 19
Joined: Thu Dec 25, 2014 8:44 pm

Re: Parallella FPGA Tutorials available

Postby yanidubin » Tue Jan 06, 2015 1:45 am

Yes, that is the issue I described above. You need to checkout a specific point in parallella-hw, because my code has not been updated for some changes they have made in the meantime. I haven't looked into it yet, but I will have cloned the system files, and some others. Meanwhile I expect they have removed some of the connections from the top level verilog, changing the interface - so the two are no longer compatible.

If you don't want to have to bring the code forwards, just do a git checkout ce97134bc01e8f3b8374e0e74b2ca191c8873f59 in parallella-hw.
Last edited by yanidubin on Tue Jan 06, 2015 12:08 pm, edited 1 time in total.
User avatar
yanidubin
 
Posts: 95
Joined: Mon Dec 17, 2012 3:23 am
Location: Christchurch, New Zealand

Re: Parallella FPGA Tutorials available

Postby steddyman » Tue Jan 06, 2015 6:39 am

That wasn't actually your code that was failing to compile. It is the standard Parallella 7020 HDMI project.
steddyman
 
Posts: 19
Joined: Thu Dec 25, 2014 8:44 pm

Re: Parallella FPGA Tutorials available

Postby steddyman » Tue Jan 06, 2015 5:40 pm

Just tried to synthesize 7020_Headless and get the same errors too.

Looks like the repo is broken.
steddyman
 
Posts: 19
Joined: Thu Dec 25, 2014 8:44 pm

Re: Parallella FPGA Tutorials available

Postby steddyman » Wed Jan 07, 2015 11:20 am

Right.. to be thorough I have done the following:

1. Create a new SUSE 64 bit VM
2. Cloned the parallella REPO directly from Github
3. Followed instructions for Tutorial 0

On the first step, when I use planAhead to copy the project.. I get the same three errors as I got under Windows:

2 x BXML file generation failed for source System
1 x Device settings for system.mp does not match with the current project

Who from parallella owns this repo that can look at it?
steddyman
 
Posts: 19
Joined: Thu Dec 25, 2014 8:44 pm

Re: Parallella FPGA Tutorials available

Postby steddyman » Wed Jan 07, 2015 7:17 pm

Right. I've finally cracked it. I have followed all the steps in the README.MD that is in the Project folder and it has worked.

The main trick seems to be having to open the XPS and fix the path to axi_hdmi_tx_16b_v1_00_a before trying to Synthesize the design.

Also had to install a bunch of extra packages on Suse to make it work.
steddyman
 
Posts: 19
Joined: Thu Dec 25, 2014 8:44 pm

Re: Parallella FPGA Tutorials available

Postby yanidubin » Wed Jan 07, 2015 9:40 pm

Hey, cool. Glad you finally got it sorted :)

This path fixup thing is likely new? Certainly never had to do this myself.
User avatar
yanidubin
 
Posts: 95
Joined: Mon Dec 17, 2012 3:23 am
Location: Christchurch, New Zealand

Re: Parallella FPGA Tutorials available

Postby steddyman » Wed Jan 07, 2015 10:54 pm

I searched google and found a reference to error I was getting on this very forum from a few months ago mentioning the readme file, so I don't think it is too long.

I think the big was unless you open the XPS first, you can't synthesise the project. Plus, I'd tried that many different things to get it to work that I probably confused steps along the way.
steddyman
 
Posts: 19
Joined: Thu Dec 25, 2014 8:44 pm

Re: Parallella FPGA Tutorials available

Postby 9600 » Thu Jan 08, 2015 7:18 am

@steddyman it would be great if you could document the steps you took to get the tools working, and then to build the projects, via the eLinux wiki. E.g. if we had a page, say, Parallella_FPGA_Build. Then the next person that comes along we can just point them at that page.

Cheers,

Andrew
Andrew Back (a.k.a. 9600 / carrierdetect)
User avatar
9600
 
Posts: 997
Joined: Mon Dec 17, 2012 3:25 am

Broken repository

Postby tif » Tue Oct 13, 2015 1:58 am

Thank you yanidubin, for your step-by-step tutorials.

Somehow there seems to be a spanner in the works.
I haven't figured out, what my personal problem is. It appears to me that the current git repository is broken. Maybe it is because I have no access to C:/home/aolofsson...
The ISE planahead project files surely got broken when moved to old/, but the Vivado project also came up with lots of files missing. Most could be resolved by changing the path from erx/ or etx/ back to elink. But a dozen files seem just not to be in the repository. Further, I have not yet figured out how to cure the script to get the external files.

What does work is the revision ce97134bc01e8f3b8374e0e74b2ca191c8873f59 with ISE. When I generate the bitstream without any changes and put it on the BOOT partition of the SD-card the unit powers up fine. But as soon as I use the gpio-dev-mem-test to access a memory location the whole system freezes and I have to do a power cycle.
Is there maybe some big-endian issue because I generate the bitstream in a Win7-VM and the copy it over to linux to do the bootgen command?

(I could not use ISE on Kubuntu as XPS did crash on start despite all the bugfixes I found on the net. I could not use Vivado either because of their stupid licensing mechanism. For me only Win7 in combination with Firefox was able to retrieve the license - not even IE did the trick.)
tif
 
Posts: 5
Joined: Thu Sep 10, 2015 3:03 am

Previous

Return to FPGA Design

Who is online

Users browsing this forum: No registered users and 5 guests