Parallella FPGA Tutorials available

Using Zynq Programmable Logic and Xilinx tools to create custom board configurations

Re: Parallella FPGA Tutorials available

Postby yanidubin » Sat Oct 11, 2014 4:01 am

Thanks Mutki - I wasn't aware of Project ARA, so thanks for mentioning that :) It would be cool indeed to have the likes of the Epiphany accessible from a smartphone.
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Re: Parallella FPGA Tutorials available

Postby shodruk » Sat Oct 11, 2014 9:14 pm

Hi Yani,
Thank you very much for sharing the tutorial.
It is very helpful for me.
I tried to follow the "Create new project" tutorial, I've found a easy way to copy version.v and XPS settings.

PlanAhead > Project Manager Window > Design Sources > Global Include,

Right Click version.v, "Copy File Into Project",

parallella_z7_top > system_stub,

Right Click system_i, "Copy File Into Project".

The files are copied to project_name.srcs/sources_1/.

I could create a new project and generate a bitstream successfully.
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Re: Parallella FPGA Tutorials available

Postby yanidubin » Sun Oct 12, 2014 1:23 am

Thanks Shodruk,

Glad it helped, and thanks for the feedback :)

I didn't know of the import method you described when I wrote Tutorial 0, and only discovered it as I was writing tutorial 3 - so I make use of it in that. I tried to go back and update this first one to use the same method, but found that when you import System (as opposed to plain Verilog files like version.v), it copies a whole bunch of extra files it simply doesn't need to - only three are required (xmp,mhs,xml). Take a look in your sources_1/imports folder immediately after using import if you want to see what I mean. But if you use the (manual) copy method once for your base project (or start from the output of the tutorial) you need not worry about this ever again - system is then already part of the project (where I think it should have been to start with), and you use the described method to import any Verilog file you are about to modify (covered in Tutorial 3).

So while there is nothing wrong with importing System using the import method (it will still build just fine), I prefer to keep my repository clean, with only the bare minimum of checked in files (no generated files), and copies minimal (hence only files being modified) to make managing merging with upstream changes (for example once we move from ISE to Vivado) simpler if few files are really being modified.

So there is a balance between sharing what I think should be common practice versus a simpler tutorial - and so I may yet change it / move it to an advanced section - because it may be I'm the only one pedantic about such things. However this tutorial was really all about settings things up "right" for repo cleanliness / removing inevitable conflicts (once you have a few projects on the go), and is already something of an "opinion piece", so it will remain as is for now.

Keep the feedback coming :)
Yani.
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Re: Parallella FPGA Tutorials available

Postby yanidubin » Sun Oct 12, 2014 11:06 am

In case anyone is wondering why I haven't posted any further tutorials (or FuseSOC pgrogress) in the last week, parallellagram.org is the reason. That is, I've been somewhat sidetracked with selecting/configuring my first hosting, and also cobbling together a lightweight blogging framework to serve up my current WordPress posts. This will make writing tutorials much simpler (especially now that it is mostly diffs rather than screenshots), and also allow me to some things with javascript I couldn't on free WordPress.

The site is not really live as such - but if anyone wants to take a look and give some feedback, please feel free. I expect some conversion failures still exist, but I'll smooth these out over time. Future posts will only be available on this site, and WP will receive only updates where I got things wrong. Now I can write everything comfortably in markdown, I don't wish to touch WP any further.

I expect within a few weeks I'll be closing comments on WP (but otherwise leaving stuff up for anyone who has bookmarked content ) and putting up an advisory that the latest version can be found on the new site.

P.S. You might have noticed a subtle name change. Parallellogram, while being a conjugation of Parallella (obvious) and Gram ("a thing drawn or written"), and also an obvious play on Parallelogram (the shape), I realised was going to look too much like a simple mis-spelling of Parallelogram (especially to anyone not acquainted with the Parallella). So I have gone for Parallellagram instead - which might improve on this slightly?
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Re: Parallella FPGA Tutorials available

Postby shodruk » Sun Oct 12, 2014 11:44 am

Thanks Yani,
I understand.
I look forward to your next article. :)
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Re: Parallella FPGA Tutorials available

Postby yanidubin » Tue Oct 14, 2014 9:54 am

Tutorial 2 is now up - this provides instructions on creating/connecting an IP Core using the AXI4 interface to communicate with the ARM. This is more suited to a larger chunk of memory (BRAM), compared with the limited register set based approach seen last time with AXI4Lite.

Not particularly exciting in and of itself - but certainly if you have an idea of what you want to do with it, you have all you need there.

I realise I need to write up the sequels for Tutorials 1 and 2. I have taken these further, but put them down about 2 months back (I have been busy writing tutorials, migrating to a new hosting solution, and porting FuseSOC). For AXI4Lite, I threw together a (very) basic ALU. For AXI4, I implemented an image smoothing algorithm.

So I will revisit these projects, get them into a reasonable state, and make an instructional tutorial for each. With these will come python scripts for on-target testing, as that is what I use myself during development. Loading in pixels one at a time is for suckers :)

Beyond that, I might investigate / cover a better tool for loading arrays of data into/out of the FPGA / reading back. The tool I've appropriated to date is really not suited to the task. After that? Nothing planned as yet. Hopefully AXI4-Stream when I have it working - but haven't been looking into this for a good month or more.
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Re: Parallella FPGA Tutorials available

Postby Melkhior » Sun Nov 09, 2014 2:59 pm

yanidubin wrote:Keep the feedback coming :)


First, thank you, your tutorials are very useful to beginners (at least, they are to me).

Some notes up to my current step - step 0 ;-)
1) Newbies could use a brief explanation of what tools like planAhead or XSP are, along with some of the vocabulary (netlist?). I understand it's an introduction to the Parallella's FPGA and not to FPGA / Xilinx tools themselves, but that could be useful to complete newbies;
2) A mention to look for the Webpack ISE, as it comes with a free license (same rational);
3) On linux, the Xilinx tools don't like localization. Unset all LC_* and LANG variables prior to launching the tools;
4) I ended up linking gmake to make; not sure if it is actually needed (it was an advice for some XPS issues).
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Re: Parallella FPGA Tutorials available

Postby Melkhior » Fri Nov 21, 2014 4:34 pm

yanidubin wrote:Keep the feedback coming :)


Another round of thanks after using tutorial 1 - my Zynq 7010 is now doing sums. There's no way I would have gotten that far without your tutorials.

Now I just need to plug-in a VHDL GF(2^m) multiplier I found on the web :-)

Following that, moving to the full AXI4 interface which is apparently faster.
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Re: Parallella FPGA Tutorials available

Postby aolofsson » Fri Nov 21, 2014 4:42 pm

Thanks for sharing you success story! A great example showing the power of openness and sharing.
Andreas
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Re: Parallella FPGA Tutorials available

Postby yanidubin » Tue Dec 02, 2014 9:30 am

Hi Melkhior,

Sorry about the slow reply - I thought I had replied, but hadn't.

Melkhior wrote:First, thank you, your tutorials are very useful to beginners (at least, they are to me).


That's great - you are welcome :) Thanks for your feedback - that will help me improve things for others.

Melkhior wrote:1) Newbies could use a brief explanation of what tools like planAhead or XSP are, along with some of the vocabulary (netlist?). I understand it's an introduction to the Parallella's FPGA and not to FPGA / Xilinx tools themselves, but that could be useful to complete newbies;

I think you are right. I'm sure this will have been covered many times over already (and better than I can), so what I should do is look around for a good really basic (and relevant) intro and recommend this for those coming in at such a level.

Melkhior wrote:2) A mention to look for the Webpack ISE, as it comes with a free license (same rational);

Good point - I take too much for granted. Will make a quick mention of this.

Melkhior wrote:3) On linux, the Xilinx tools don't like localization. Unset all LC_* and LANG variables prior to launching the tools;

This sounds like a misconfiguration. I say this because It Works For Me (tm). It could well be a common issue (depending which distro you use, and if customisation has caused the issue rather than the distro itself). The distro I use is only semi-mainstream (ArchLinux), so it could well be that more people are affected by this than not. I'll make a note of this now I know about it.

Melkhior wrote:4) I ended up linking gmake to make; not sure if it is actually needed (it was an advice for some XPS issues).

I have indeed done this on my box, and did so because it was needed.

Thanks again for the feedback - I'll aim to update the tutorial soon.
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