Parallella Community

Hi Guys,

I have managed to add AXI peripherals using XPS on the hdmi project and everything works fine.

When I do the same on the headless project though I get the following critical warnings:

[Constraints 18-11] Could not find cell or net 'axi_interconnect_1/*_converter_bank/*clock_conv_inst/*asyncfifo_*/*mem/*dout_i_???' [C:/Development/parallella/Fpga/parallella-hw/fpga/edk/parallella_7020_headless/implementation/system_axi_interconnect_1_wrapper.ncf:6]
[Constraints 18-11] Could not find cell or net 'axi_interconnect_1/*_converter_bank/*clock_conv_inst/*asyncfifo_*/*mem/*dout_i_????' [C:/Development/parallella/Fpga/parallella-hw/fpga/edk/parallella_7020_headless/implementation/system_axi_interconnect_1_wrapper.ncf:7]

If I run through the implementation and generate the bitstream it loads ok but when I try to read from the AXI bus from a linux app the parallella hangs totally, so I guess these warnings are important

I have been banging my head against the wall for a couple of days over this, does anyone have any pointers of where to look to find the problem?

Thanks

Andy

If you look in the Warnings tab in XPS, you probably get warnings of the sort:

WARNING:EDK:4059 - INSTANCE: processing_system7_0, Overriding connection of
PORT: M_AXI_GP1_RDATA, VALUE: processing_system7_0_M_AXI_GP1_RDATA - which is
part of the connected BUSIF: M_AXI_GP1 -
/stash/files/dev/embedded/parallella/parallella-fpga-tutorials/Tutorial001_AX
I4Lite/Tutorial001_AXI4Lite.srcs/sources_1/system/system.mhs line 115

I believe this is conflicting with the eLink.

I think I have confirmed my theory ( is the ref since this was cross-posted) from last night that the GP0/GP1 is your issue. For example, if you do a diff on the system.mhs for the headless and hdmi projects, you will notice that the hdmi IP core already uses GP0, so it is already enabled, and I guess XPS happens to stick the IPCore on this bus (by default)

parallella-hw$ diff fpga/edk/parallella_7020_{headless,hdmi}/system.mhs | grep M_AXI_GP0
> PARAMETER C_USE_M_AXI_GP0 = 1
> BUS_INTERFACE M_AXI_GP0 = axi_interconnect_1
> PORT M_AXI_GP0_ACLK = processing_system7_0_FCLK_CLK0_0

Hi Yani,

Thanks very much for your help and pointers.

Well I have spent another couple of hours trying to get this to work and have failed in a variety of ways!

I think I will carry on using the hdmi project and wait for your tutorial on how to set up the headless project.

Cheers

Andu

Hi Andy,

Sorry it took a while - you can find it at the new thread I've started for my tutorials so that questions/feedback can all be in the same place.

Hopefully that helps you. If not, (or anyway) I recommend diffing the whole system.mhs you have, and the one from my project here: https://github.com/yanidubin/parallella ... system.mhs.

I find it is often something like the clocks misbehaving. Indeed, I already had to redo the tutorial in a roundabout way as I discovered Xilinx didn't properly handle having the PCore added, then shifted to GP0 once that was avialable. It allowed the bus assignment, but wouldn't hook up the clock.

I am not a big fan of Xilinx today - I tried running through the (already workaround) steps today, and they kept inexplicably failing. By diffing the system.mhs I could see it was randomly deleting some of my clock definitions, but had no idea why. After some hours of frustration (it was so easy the first time!), I restarted XPS, and the same thing which had been failing suddenly behaved.

Anyways, I always refer to system.mhs when I want to see what the tool has really changed, or what differs between projects. I'm not really a UI guy myself, and it is times like this I feel justified hacking it by hand.

Hi Yani,

I cannot see the tutorial 1 on the blog site, is it done yet?

I know what you mean by the Xilinx tools, I think I have been spoiled as a software developer. I pity people that have to use these tools for their job!

I will have another fumble and see how the mhs files differ...

Cheers

Andy

*facepalm* Oh dear, I forgot to make it public. Try now

Nice one thanks.

I can be your first tester

Hi Yani,

Ok I followed your example and hit one of the problems I have been getting.

When I go to set the bus for M_AXI_GP0 the only bus I can choose is axi_interconnect_0.

The only way around this is to add the IP core before doing this and then I get loads of other issues.

How do you get axi_interconnect_1 to appear before adding the ip core?

Cheers

Andy

Interesting that you have an axi_interconnect_0 already. Is this a fresh system.mhs from the parallella-hw repo?

Well, you should get the options for existing interconnects (axi_interconnect_0 in your case), as well as "No Connection" and "New Connection". Do you get an option "New Connection"? If you choose that, I believe it will create axi_interconnect_1.

But actually the name of the interconnect is immaterial - I am not sure why you got 0, and I got 1 - maybe one of us did something a bit differently.

The only important thing is that you have an interconnect with both the correct master and the correct peripheral attached to it.

Hi Yani,

The problem is I always seem to end up with two of the buggers

axi_interconnect_0 is not there when I start.

When I add a new connection on M_AXI_GP0 then axi_interconnect_0 is created.

Now when I add my ip core axi_interconnect_1 is created, and M_AXI_GP1 is connected to it as well as the new ip core.

Then it all gets very confusing.