Parallella Community

HI,

Recently I've tested again running the planAhead (from Ise WebPack 14.7 IIRC) on the Parallella supplied sources (including the AD HDMI interface), changed some things (in this case about some of the GPIO pins), loaded in the new bit.bin file, and tested the result to work, which is fine.

However now I'd like to do a bit more communication with the FPGA pins than the GPIO allows, for instance by adding a simple ARM-FPGA link with registers (like the Xilinx software can generate), or possible by defining new messages or communication end-points in the existing ARM<->Epiphany link with fifos, word width adaptations and flow control.

Did anyone work on this or know by heart if it is possible to add a simple (like the Xilinx examples) interface to the existing ones, without breaking the alrready working system ?

Also, is it easy enough to follow the OS support for the Epiphany to add stuff or add an additional interface to the kernel device tree or something ?

Thanks,

Theo V.

I'm about to do the same so every information is apreciated

Hi guys - are you still seeking assistance with this? I have been successful in this area. I started by finding some tutorials for the Zedboard (which really just refer you to the core generation wizard), and working out how this process needed to be adapted for the Parallella (as to your question about breaking an already working system - I think if you followed the Zedboard tutorial rather than working out the differences, you might struggle with that). The process should only take an hour or so to follow through. It also covers use of the xps tool, which leads to other fun stuff such as mapping SPI/UART/I2C via the FPGA GPIO to daughter cards - but that is another tutorial.

If there is interest, I would be willing to write a tutorial showing the steps to use in the wizard, the diffs showing helpful modifications to take the output of this and alter it so you can write a value and get a result back to show the FPGA has worked on the data. I can also include an example python test script to exercise the core (write value, read result, and compare to ensure correctness). I'll either include the process for runtime reconfiguration of the FPGA as instructions or part of the script.

The two interfaces I have been successful with use the /dev/mem memory mapped IO. This is the most basic approach which requires no development of your own driver kernel module.

I can cover both, since there is very little difference other than the checkboxes in the wizard.

The first uses AXI4Lite to expose a bunch of registers. To brush up on my VHDL, implemented a basic ALU, giving each of the registers an operand/instruction/result role.

The second uses full AXI4, and provides a means to write values to /dev/mem, and have them pulled into BRAM on the FPGA. After testing this with the same ALU, I decided to make an application which made use of the expanded addressable memory space provided - so I'm still perfecting a smoothing filter which runs on an 8x8 matrix of 8-bit grayscale pixel values and returns the result.

Would you (or anyone?) be interested? I believe I could have something up within a week or so.

that sounds very interesting to me, a tutorial/howto would be great!

Okay, cool - I will get to work on it soon.

+1. I think many could find this quite useful.

Cheers,

Andrew

Hi yanidubin,

Have you managed to add the axi peripherals to the headless project or just the hdmi one?


Cheers

Andy

Hi AndyC - only the headless one actually. Never used the HDMI ones.

I got a little side-tracked writing a pre-requisite tutorial, which I think is necessary before beginning. The actual tutorial shouldn't take much longer, now I finally have this out of the way and properly tested.
So I'm posting a link to in the meantime. I expect to have the tutorial up in a day's time, as it is getting late here in NZ.

This is my first blog / public tutorial, and I'm struggling with the limitations of free wordpress (no scripting, very little customisation - despite what, I gather, wordpress offers when properly hosted). As I don't have my own hosting as such, this will have to do for now.

Any feedback is welcome. I am already aware that brevity is not my strong point.

Ah Super, just the man I need to talk to

I have had no luck at all adding AXI peripherals to the headless 7020 project while it works fine in the 7020 hdmi project.

I get the following warnings:

[Constraints 18-11] Could not find cell or net 'axi_interconnect_1/*_converter_bank/*clock_conv_inst/*asyncfifo_*/*mem/*dout_i_???' [C:/Development/parallella/Fpga/parallella-hw/fpga/edk/parallella_7020_headless/implementation/system_axi_interconnect_1_wrapper.ncf:6]
[Constraints 18-11] Could not find cell or net 'axi_interconnect_1/*_converter_bank/*clock_conv_inst/*asyncfifo_*/*mem/*dout_i_????' [C:/Development/parallella/Fpga/parallella-hw/fpga/edk/parallella_7020_headless/implementation/system_axi_interconnect_1_wrapper.ncf:7]

If I run through the implementation and generate the bitstream it loads ok but when I try to read from the AXI bus from a linux app the parallella hangs totally, so I guess these warnings are important.

Did you do anything special setting the AXI bus up?

Cheers

Andy