I'm interested in creating a small timing circuit in the PL fabric to minimize clock drift in high load situations.
I know that a hardware RTC can be had cheaply, but this seems like a good project to start understanding how to implement custom circuits in the Parallella.
I have found a few VHDL examples of RTC like systems and it's very simple to implement, but what I have found has been making a counter, and then outputting the time data to a 7-segment LCD. In the Parallella this data would need to make its way into the Linux kernel.
I'm a complete novice with FPGA development and integration. For those of you with some experience with this, what is the best way for me to get that data into the rest of the system?
