openPOWERLINK on Parallella

Using Zynq Programmable Logic and Xilinx tools to create custom board configurations

openPOWERLINK on Parallella

Postby pedro_nf » Fri Jun 27, 2014 1:45 pm

hello everyone,
can someone tell me if it is possible to put this inside the Parallella FPGA?

sorry for my ignorance, I'm willing to learn about FPGA programming but it will take a while...

ho and if someone already done this or is willing to, please let me know!

thanks in advance
Pedro Ferreira
"there are 10 types of people, those who understand binary and those who don't!"
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Re: openPOWERLINK on Parallella

Postby yanidubin » Thu Oct 02, 2014 10:33 am

I don't have much in the way of answers (not an FPGA guy either), but can suggest some of the questions which I would be seeking to address - and maybe someone else on here can answer some of them, or put you on the right track if my questions are the wrong ones.

According to roadmap for the project page for this, they are planning on adding Zynq support by November this year. This page on the other hand suggests it has been supported since April of last year. Not strictly required - but helpful to know if it has been gotten running on a similar reference platform. If someone has done it on the zedboard, for instance, that would be very helpful.

It uses AXI Interconnect which is available on the platform already (as opposed to, say, wishbone), which is good. It would be good to know if there are any speed requirements on this. Much of the FPGA is currently clocked very low - I gather there is more FPGA development to do to get it stable at higher frequencies. While I gather you can drive the IPCore itself at whatever frequency it is able to run at on this device, where this connects to other parts (such as the AXI bus), there may be implications.

There is the question of how much space it requires (will it run on the 7020, and will it run on the 7010). My second link above suggests this has been tested on a ZC702, which is a 7020 based board. It also says it has been tested with the stack both running on the Arm, and running on the FPGA. You may find one or both approaches fits on the 7010 also.

I don't know anything about industrial ethernet - so sorry if this is a clueless question. I am not sure if it connects to the existing PHY, or would you be bringing it out via an expansion board? In the former case, I believe it is possible to reroute (most) MIO pins to the FPGA fabric, meaning if you do intend to interface the IPCore to the existing PHY (via *MII), connectivity should be (disabling ETH0 and rerouting the MIO pins so you can connect *MII on IPCore to PHY chip). You would need to confirm that the 100Mbit PHY present on the board is adequate.

Then it is mostly software (will the drivers work with the kernel, or is there work to do there).
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