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The top level module is chosen by the designer - it defaults to the top of the design tree, or you can right click on a sub-module and select "set as top module". You might need to change the default if you were testing a subcomponent, or had a large design that spanned multiple FPGAs

It is the inputs and outputs of this module that gets connected to the external pins of the FPGA (or to the internal connections to the ARM cores).

To be precise, C's main() function is being called from the C Runtime (aka CRT0). The CRT is a wrapper around your program that handles the initialization of the state of the program and environment. After initializing interrupt vector, global and static variables, etc. it calls main(). Upon return from main(), the CRT's exit() procedures takes care of cleanup.

CRT0 itself is called by the SYNC Interrupt, which is fired upon reset. The first function is the start() function, which is the interrupt handler for the SYNC event (IRQ 0).

You can have a look at CRT0 here:

https://github.com/adapteva/epiphany-ne ... any/crt0.S