Hi rec,
Please see the github repository . This has fpga projects for the board including all the constraints files, see the README for the directory structure and what's where. These projects use the Xilinx tools PlanAhead and XPS, though we'll be moving to Vivado at some point. You can get a free WebPack license for these tools from Xilinx.
As long as you start with the constraints and top-level IOs provided there is no risk of damage, but for example redefining inputs as outputs which then contend with outputs from other components risks damage to the FPGA, the external component, or maybe both. In general all these components are fairly tough but it's always better not to test them. A bit of care when making changes is worth the time.
-Fred