Parallella Community

Problems that have this high a rate of occurrence don't happen because of unknown voodoo or a passing alpha particle, but because of quantifiable causes such as incorrect power sequencing, or out of spec rise times, or external devices not being held in reset while the FPGA is configuring its GPIOs, or race conditions, or noise on lines, or reflections owing to impedance mismatch, or inadequate on-board voltage regulation / current starvation on power-up surges, or etc etc etc .... you get the idea. There are a lot of possible causes, many more than I've mentioned.

Note that even if the board design is essentially correct, it's clear from the error rate that the chosen design margins are insufficient for reliable operation.

The feedback to Andreas about how often users find USB to be non-operational after boot is interesting as an indicator of individual experiences, but it probably won't do much to narrow down the cause. That's going to require some good old-fashioned engineering legwork with sampling scopes, logic analysers and other instrumentation, and meticulous re-examination of datasheets. There's also a prerequisite --- the Adapteva engineers first need a System Under Test that fails regularly, otherwise fault inspection is really hard and slow.

Am I right in thinking that such a reliably failing system is not yet to hand? If it were, I suspect Adapteva wouldn't be asking these questions at all, they'd just be getting on with diagnosing the cause, and then correcting the board design so that the situation does not occur.

Morgaine.

RS replaces faulty items without any problems.