Hi,
I am trying to understand the Memory architecture of Parallella. Unfortunately I have less knowledge of VHDL and can not readout details from hw files. I will be grateful for comments if I misunderstand something.
According to documentation and posts I could summarize:
There are 3 sorts of RAM available in system [2]
1. Host Ram
Q1. Is it "O/S DRAM" from Figure 4. Reference Manual (marked as Off-Chip), or On-Chip Memory described in Ch.29 Zynq-7000 Technical reference manual ? Where can I find the details about this memory. Size, address, accessibility etc.
2. Shared Ram
Shared RAM memory - 1 GB 32-bit - accessible for both Dual-core ARM and each epiphany core
Described as SHARED DRAM on Figure 4. Reference Manual
3. Epiphany local Ram
16 x 32 kB accessible for Dual-core ARM and each epiphany core
Described as Epiphany on Figure 4. Reference Manual
Dataflow:
Q2. Data between epiphany cores is exchanged via rMesh and cMesh. It might be also exchanged via shared Ram, but it does not have a lot of sense considering bad performance.
"The Epiphany coprocessor is connected to the Zynq SOC via the 48-pin eLink interface" [1].
Q3. Does eLink interface have anything to do with eMesh NOC ? If not, how are the data transferred from elink to particular epiphany core ?
Q4. Data exchange between Epiphany and Shared Ram goes through eLink<->FPGA<->MEM-CTRL<->Shared Ram without any ARM DualCore interaction ?
Q5. All data exchange possibilities between ARM DualCore and Epiphany are :
- ARM can send binary (code and data) to epiphany via eLink
- ARM can read Epiphany local Ram via eLink
- ARM can read/write to shared memory via MEM-CTRL
- Epiphany can read/write to shared memory according to Q4
- Epiphany can not read/write from/to Host Ram
References:
[1] Epiphany Architecture Reference
[2] ()