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Parallella Community Supercomputing for Everyone 2020-03-28T13:45:27+00:00 https://parallella.org/forums/feed.php?f=51 2020-03-28T13:45:27+00:00 2020-03-28T13:45:27+00:00 https://parallella.org/forums/viewtopic.php?t=4365&p=20161#p20161 <![CDATA[FPGA Design • Re: Figuring out where addresses comes from?]]> http://mkaczanowski.com/parallella-part-3-kernel/

Statistics: Posted by mkaczanowski — Sat Mar 28, 2020 1:45 pm

]]> 2020-02-17T20:47:25+00:00 2020-02-17T20:47:25+00:00 https://parallella.org/forums/viewtopic.php?t=4365&p=20159#p20159 <![CDATA[FPGA Design • Figuring out where addresses comes from?]]> I don't have much knowledge about the FPGA, so I tried to understand parallella design a bit more by looking at Vivado project and kernel module sources.

There are a few addresses there:
1. parallella_slave_axi - 0x80000000
2. memory range owned by kernel:
```
/* First range is FPGA config regs.
* Second range is mappable emesh region
*/
reg = <0x81000000 0x100000>, <0x80000000 0x10000000>;
```
3. mmu setting
adapteva,mmu = <0x8e000000 0x3e000000 0x02000000>;
emesh_start, phys_start, size
```

So I am trying to figure where each address came from:
1. axi_slave address (0x80000000) is CPU memory mapped, so no questions here
2. FPGA Config regs, offset: 0x81000000 - I don't quite get why offset is set to 0x81000000 and where is it defined?
In the C library the 0x81000000 is used as eLink base and that makes a lot of sense, however where it's defined in verilog that eLink should be placed at this address? I only found the relative addressing: https://github.com/aolofsson/oh/blob/ma ... _regmap.vh
3. mappable eMesh region = offset: 0x80000000, size: 0x10000000. I think I understand that as: 4 elinks (west, north, ...) * 64 cores * (1<<20) mappable memory per core
4. MMU / shared memory - there is 32mb of shared DRAM. Where emesh_start: 0x8e000000 and phys: 0x3e000000 comes from?

If you could help me figure out where this addressing comes from (mostly the base addresses, that would be helpful)

Thanks,
Mateusz

Statistics: Posted by mkaczanowski — Mon Feb 17, 2020 8:47 pm

]]> 2020-02-17T20:13:04+00:00 2020-02-17T20:13:04+00:00 https://parallella.org/forums/viewtopic.php?t=4364&p=20158#p20158 <![CDATA[FPGA Design • Re: Generate bitstream with Vivado 2019.x]]> Statistics: Posted by mkaczanowski — Mon Feb 17, 2020 8:13 pm

]]> 2020-02-12T00:24:19+00:00 2020-02-12T00:24:19+00:00 https://parallella.org/forums/viewtopic.php?t=4364&p=20157#p20157 <![CDATA[FPGA Design • Re: Generate bitstream with Vivado 2019.x]]> https://github.com/olajep/oh.git

That version is for Vivado 2018.2. You need to edit the block design scripts:
https://github.com/olajep/oh/blob/b57c7 ... bd.tcl#L23
https://github.com/olajep/oh/blob/b57c7 ... bd.tcl#L23
https://github.com/olajep/oh/blob/b57c7 ... bd.tcl#L23
https://github.com/olajep/oh/blob/b57c7 ... bd.tcl#L23


The ADI IP's require Vivado 2018.2 so the HDMI bitstream builds will likely break.
You should be able to override that with "export ADI_IGNORE_VERSION_CHECK"

HTH,
Ola

Statistics: Posted by olajep — Wed Feb 12, 2020 12:24 am

]]> 2020-02-10T22:31:27+00:00 2020-02-10T22:31:27+00:00 https://parallella.org/forums/viewtopic.php?t=4364&p=20156#p20156 <![CDATA[FPGA Design • Generate bitstream with Vivado 2019.x]]> Statistics: Posted by mkaczanowski — Mon Feb 10, 2020 10:31 pm

]]> 2020-01-08T17:16:55+00:00 2020-01-08T17:16:55+00:00 https://parallella.org/forums/viewtopic.php?t=4362&p=20154#p20154 <![CDATA[FPGA Design • Re: Vivado(_hls) 2019.2 , Anyone ?]]> Statistics: Posted by theover — Wed Jan 08, 2020 5:16 pm

]]> 2020-01-08T16:55:05+00:00 2020-01-08T16:55:05+00:00 https://parallella.org/forums/viewtopic.php?t=4362&p=20153#p20153 <![CDATA[FPGA Design • Re: Vivado(_hls) 2019.2 , Anyone ?]]> Statistics: Posted by ajtravis — Wed Jan 08, 2020 4:55 pm

]]> 2020-01-08T14:50:18+00:00 2020-01-08T14:50:18+00:00 https://parallella.org/forums/viewtopic.php?t=4362&p=20152#p20152 <![CDATA[FPGA Design • Re: Vivado(_hls) 2019.2 , Anyone ?]]>
"Vivado HLS demonstration C function to FPGA"

Cheers,

Theo V.

Statistics: Posted by theover — Wed Jan 08, 2020 2:50 pm

]]> 2019-12-25T15:56:48+00:00 2019-12-25T15:56:48+00:00 https://parallella.org/forums/viewtopic.php?t=4362&p=20151#p20151 <![CDATA[FPGA Design • Re: Vivado(_hls) 2019.2 , Anyone ?]]> Statistics: Posted by ajtravis — Wed Dec 25, 2019 3:56 pm

]]> 2019-12-25T15:29:23+00:00 2019-12-25T15:29:23+00:00 https://parallella.org/forums/viewtopic.php?t=4362&p=20150#p20150 <![CDATA[FPGA Design • Re: Vivado(_hls) 2019.2 , Anyone ?]]> Statistics: Posted by theover — Wed Dec 25, 2019 3:29 pm

]]> 2019-12-07T20:00:14+00:00 2019-12-07T20:00:14+00:00 https://parallella.org/forums/viewtopic.php?t=4362&p=20148#p20148 <![CDATA[FPGA Design • Re: Vivado(_hls) 2019.2 , Anyone ?]]> Statistics: Posted by theover — Sat Dec 07, 2019 8:00 pm

]]> 2019-12-07T15:30:37+00:00 2019-12-07T15:30:37+00:00 https://parallella.org/forums/viewtopic.php?t=4362&p=20147#p20147 <![CDATA[FPGA Design • Re: Vivado(_hls) 2019.2 , Anyone ?]]> Statistics: Posted by ajtravis — Sat Dec 07, 2019 3:30 pm

]]> 2019-12-07T12:25:11+00:00 2019-12-07T12:25:11+00:00 https://parallella.org/forums/viewtopic.php?t=4362&p=20145#p20145 <![CDATA[FPGA Design • Vivado(_hls) 2019.2 , Anyone ?]]>
Very quiet here, it almost feels like an antiquarian.

I plan to put my 7010 board to good use though with the new Vivado, which includes partial reprogramming. I've used Vivado before here, like , but it seems the high level language "Silicon Compilation" are taking off, and I like to make use of them on this cheap board before having to use for instance AWS credit for an F1 node.

Anyone try example projects on recent Vivado ?
THey seem to have just about every board as a design template, except for the Parallella, why so spartan, doesn't it sell anymore?

Theo V

Statistics: Posted by theover — Sat Dec 07, 2019 12:25 pm

]]> 2018-11-07T00:01:43+00:00 2018-11-07T00:01:43+00:00 https://parallella.org/forums/viewtopic.php?t=4297&p=20099#p20099 <![CDATA[FPGA Design • Re: creating a output register/interrup from PL to arm proce]]>
https://seguridad-agile.blogspot.com/20 ... nutos.html

Statistics: Posted by cpantel — Wed Nov 07, 2018 12:01 am

]]> 2018-10-28T20:57:44+00:00 2018-10-28T20:57:44+00:00 https://parallella.org/forums/viewtopic.php?t=4297&p=20096#p20096 <![CDATA[FPGA Design • Re: creating a output register/interrup from PL to arm proce]]>
do you remember which distro/kernel worked for you? The accelerator example opens /dev/epiphany this way

int mem_fd = -1;
//############################################
//# Map Memory Using Generic Epiphany driver
//############################################
int e_map(unsigned addr, void **ptr, unsigned *offset) {
...
//Open /dev/mem file if not already
if(mem_fd < 1) {
mem_fd = open ("/dev/epiphany", O_RDWR);
if (mem_fd < 1) {
perror("f_map");
return -1;
}
}

but in these distros

parabuntu-2016.11.1-headless-z7010.img
ubuntu-15.04-esdk-2016.3-headless-z7010.img

/dev/epiphany is a folder with some content:

elink0
mesh0


I could not make work this one yet:
ubuntu-14.04-headless-z7010-20150130.1.img


Any hints?

Statistics: Posted by cpantel — Sun Oct 28, 2018 8:57 pm

]]>