Setting Parallela RISC-V environment You must source this script ${TOP} was set to /home/promach/Documents/Grive/Personal/Digital/Parallella/parallella-riscv $SCRIPTS directory was set to /home/promach/Documents/Grive/Personal/Digital/Parallella/parallella-riscv/scripts $BOOT directory was set to /home/promach/Documents/Grive/Personal/Digital/Parallella/parallella-riscv/boot $ROCKETCHIP directory was set to /home/promach/Documents/Grive/Personal/Digital/Parallella/parallella-riscv/ip/rocket-chip $RISCVTOOLS directory was set to /home/promach/Documents/Grive/Personal/Digital/Parallella/parallella-riscv/ip/rocket-chip/riscv-tools $RISCV directory was set to /home/promach/Documents/Grive/Personal/Digital/Parallella/parallella-riscv/ip/toolchain $PATH extended with /home/promach/Documents/Grive/Personal/Digital/Parallella/parallella-riscv/ip/toolchain/bin $BOARD set to parallella $JOBS set to 8 Vivado path set to /opt/Xilinx/Vivado Vivado version set to 2017.1 sed -i "s/^\(\`define RISCV_CORE_ARCH_\)[a-zA-Z0-9]*/\1RV64IMA/" /home/promach/Documents/Grive/Personal/Digital/Parallella/parallella-riscv/ip/"RISCV_Rocket_Core_RV64_1.0"/src/settings.vh sed -i "s/^\(\`define RISCV_DRAM_BASE\) [0-9]\'d[0-9]/\1 "3\'d1"/" /home/promach/Documents/Grive/Personal/Digital/Parallella/parallella-riscv/ip/"RISCV_Rocket_Core_RV64_1.0"/src/settings.vh sed -i "s/^\(\`define RISCV_DRAM_BITS\) [0-9]\{2\}/\1 29/" /home/promach/Documents/Grive/Personal/Digital/Parallella/parallella-riscv/ip/"RISCV_Rocket_Core_RV64_1.0"/src/settings.vh sed -i "s/^\(\`include \"\)[a-zA-Z0-9]*\(\.Core\.vh\"\)/\1RV64IMA\2/" /home/promach/Documents/Grive/Personal/Digital/Parallella/parallella-riscv/ip/"RISCV_Rocket_Core_RV64_1.0"/src/RV64.Core.v cd /home/promach/Documents/Grive/Personal/Digital/Parallella/parallella-riscv/parallella/fpga && \ rm -rf riscv_rv64 && \ export BOARD_DEVICE=xc7z010clg400-1 && \ export BOARD_PART= && \ export RISCV_CORE_ARCH=RV64IMA && \ vivado -mode tcl -source /home/promach/Documents/Grive/Personal/Digital/Parallella/parallella-riscv/parallella/fpga/ip_package_riscv.tcl ****** Vivado v2017.1 (64-bit) **** SW Build 1846317 on Fri Apr 14 18:54:47 MDT 2017 **** IP Build 1846188 on Fri Apr 14 20:52:08 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /home/promach/Documents/Grive/Personal/Digital/Parallella/parallella-riscv/parallella/fpga/ip_package_riscv.tcl # source ./ip_params_riscv.tcl ## set design riscv_rv64 ## set projdir ./riscv_rv64/ ## set root "../../parallella" ## set partname $::env(BOARD_DEVICE) ## set boardpart $::env(BOARD_PART) ## set hdl_files [list \ ## $root/hdl/riscv.rv64/ \ ## ] ## set ip_files [] ## set constraints_files [] ## set clk_m_axi "m_axi_aclk" ## set clk_s_axi "s_axi_aclk" # source ../../scripts/vivado/create_ip.tcl ## create_project -force $design $projdir -part $partname ## set_property target_language Verilog [current_project] ## set_property source_mgmt_mode None [current_project] ## if {$boardpart != ""} { ## set_property "board_part" $boardpart [current_project] ## } ## if {[string equal [get_filesets -quiet sources_1] ""]} { ## create_fileset -srcset sources_1 ## } ## add_files -norecurse -fileset [get_filesets sources_1] $hdl_files ## set_property top $design [get_filesets sources_1] ## if {[string equal [get_filesets -quiet constraints_1] ""]} { ## create_fileset -constrset constraints_1 ## } ## if {[llength $constraints_files] != 0} { ## add_files -norecurse -fileset [get_filesets constraints_1] $constraints_files ## } ## if {[llength $ip_files] != 0} { ## ## #Add to fileset ## add_files -norecurse -fileset [get_filesets sources_1] $ip_files ## ## #Set mode for IP ## foreach file $ip_files { ## #TODO: is this needed? ## set file_obj [get_files -of_objects [get_filesets sources_1] $file] ## #set_property "synth_checkpoint_mode" "Singular" $file_obj ## } ## #RERUN/UPGRADE IP ## upgrade_ip [get_ips] ## } ## ipx::package_project -import_files -force_update_compile_order -force -root_dir $projdir CRITICAL WARNING: [filemgmt 20-742] The top module "riscv_rv64" specified for this project can not be validated. The current project is using automatic hierarchy update mode, and hence a new suitable replacement top will be automatically selected. If this is not desired, please change the hierarchy update mode to one of the manual compile order modes first, and then set top to any desired value. Resolution: To switch to manual update order go to the Sources view, right-click on any node in the hierarchy and in the context menu select: 'Hierarchy Update' option 'No Update' or run the following Tcl Command: set_property source_mgmt_mode None [current_project] (which is the Manual Compile Order mode). WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/parallella-riscv/parallella/hdl/riscv.rv64/RV64.Core.v'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/parallella-riscv/parallella/hdl/riscv.rv64/RV64IMAFD.Core.vh'. WARNING: [IP_Flow 19-3899] Cannot get the environment domain name variable for the component vendor name. Setting the vendor name to 'user.org'. INFO: [IP_Flow 19-1842] HDL Parser: Found include file "src/settings.vh" from the top-level HDL file. INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2017.1/data/ip'. INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository). INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository). INFO: [IP_Flow 19-4753] Inferred signal 'reset' from port 's_axi_aresetn' as interface 's_axi_aresetn'. INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. INFO: [IP_Flow 19-4753] Inferred signal 'reset' from port 'm_axi_aresetn' as interface 'm_axi_aresetn'. INFO: [IP_Flow 19-4728] Bus Interface 'm_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. INFO: [IP_Flow 19-4753] Inferred signal 'clock' from port 's_axi_aclk' as interface 's_axi_aclk'. INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. INFO: [IP_Flow 19-4753] Inferred signal 'clock' from port 'm_axi_aclk' as interface 'm_axi_aclk'. INFO: [IP_Flow 19-4728] Bus Interface 'm_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 'm_axi'. INFO: [IP_Flow 19-4728] Bus Interface 'm_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 'm_axi_aresetn'. INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'. ## ipx::associate_bus_interfaces -busif s_axi -clock $clk_s_axi [ipx::current_core] ## ipx::associate_bus_interfaces -busif m_axi -clock $clk_m_axi [ipx::current_core] ## ipx::remove_memory_map {s_axi} [ipx::current_core] ## ipx::add_memory_map {s_axi} [ipx::current_core] ## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] ## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] ## set_property range {65536} [ipx::get_address_blocks axi_lite -of_objects \ ## [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] ## set_property vendor {www.parallella.org} [ipx::current_core] ## set_property library {user} [ipx::current_core] ## set_property taxonomy {{/AXI_Infrastructure}} [ipx::current_core] ## set_property vendor_display_name {ADAPTEVA} [ipx::current_core] ## set_property company_url {www.parallella.org} [ipx::current_core] ## set_property supported_families { \ ## {virtex7} {Production} \ ## {qvirtex7} {Production} \ ## {kintex7} {Production} \ ## {kintex7l} {Production} \ ## {qkintex7} {Production} \ ## {qkintex7l} {Production} \ ## {artix7} {Production} \ ## {artix7l} {Production} \ ## {aartix7} {Production} \ ## {qartix7} {Production} \ ## {zynq} {Production} \ ## {qzynq} {Production} \ ## {azynq} {Production} \ ## } [ipx::current_core] WARNING: [IP_Flow 19-4623] Unrecognized family virtex7. Please verify spelling and reissue command to set the supported files. WARNING: [IP_Flow 19-4623] Unrecognized family qvirtex7. Please verify spelling and reissue command to set the supported files. WARNING: [IP_Flow 19-4623] Unrecognized family qkintex7. Please verify spelling and reissue command to set the supported files. WARNING: [IP_Flow 19-4623] Unrecognized family qkintex7l. Please verify spelling and reissue command to set the supported files. WARNING: [IP_Flow 19-4623] Unrecognized family qartix7. Please verify spelling and reissue command to set the supported files. WARNING: [IP_Flow 19-4623] Unrecognized family qzynq. Please verify spelling and reissue command to set the supported files. ## ipx::create_xgui_files [ipx::current_core] ## ipx::update_checksums [ipx::current_core] ## ipx::save_core [ipx::current_core] ## ipx::check_integrity -quiet [ipx::current_core] ## ipx::archive_core [concat $projdir/$design.zip] [ipx::current_core] ## exit INFO: [Common 17-206] Exiting Vivado at Thu May 25 14:14:07 2017... sed -i "s/^\(set scripts_vivado_version \)[0-9]\{4\}\.[0-9]/\12017.1/" /home/promach/Documents/Grive/Personal/Digital/Parallella/parallella-riscv/parallella/fpga/system_bd.tcl cd /home/promach/Documents/Grive/Personal/Digital/Parallella/parallella-riscv/parallella/fpga && \ rm -rf parallella_riscv && \ export BOARD_DEVICE=xc7z010clg400-1 && \ export BOARD_PART= && \ export RISCV_CORE_ARCH=RV64IMA && \ vivado -mode tcl -source /home/promach/Documents/Grive/Personal/Digital/Parallella/parallella-riscv/parallella/fpga/system_bitstream.tcl && \ cp ./parallella_riscv/system.runs/impl_1/system_wrapper.bit /home/promach/Documents/Grive/Personal/Digital/Parallella/parallella-riscv/parallella/fpga/parallella.bit ****** Vivado v2017.1 (64-bit) **** SW Build 1846317 on Fri Apr 14 18:54:47 MDT 2017 **** IP Build 1846188 on Fri Apr 14 20:52:08 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /home/promach/Documents/Grive/Personal/Digital/Parallella/parallella-riscv/parallella/fpga/system_bitstream.tcl # source ./system_params.tcl ## set design system ## set projdir ./parallella_riscv/ ## set parallella "../../parallella/oh" ## set partname $::env(BOARD_DEVICE) ## set boardpart $::env(BOARD_PART) ## set ip_repos [list \ ## "./parallella_base" \ ## "./riscv_rv64" \ ## ] ## set hdl_files [] ## set constraints_files [list \ ## ${parallella}/parallella/fpga/parallella_timing.xdc \ ## ${parallella}/parallella/fpga/parallella_io.xdc \ ## ] ## if {$partname == "xc7z020clg400-1"} { ## set parallella_gpio_ports 24 ## lappend constraints_files ${parallella}/parallella/fpga/parallella_7020_io.xdc ## } ## if {$partname == "xc7z010clg400-1"} { ## set parallella_gpio_ports 12 ## } ## set riscv_core_arch $::env(RISCV_CORE_ARCH) ## if {$riscv_core_arch == "RV64IMA" } { ## set rv64_clk_jitter 151.636 ## set rv64_clk_phase_error 98.575 ## set rv64_clk_request_freq 50.000 ## set rv64_clk_multiplier 10.000 ## set rv64_clk_divider1 20.000 ## set rv64_clk_divider2 1 ## } ## if {$riscv_core_arch == "RV64IMAFD" } { ## set rv64_clk_jitter 181.828 ## set rv64_clk_phase_error 104.359 ## set rv64_clk_request_freq 25.000 ## set rv64_clk_multiplier 9.125 ## set rv64_clk_divider1 36.500 ## set rv64_clk_divider2 1 ## } # source ../../scripts/vivado/system_init.tcl ## create_project -force $design $projdir -part $partname ## set_property target_language Verilog [current_project] ## if {$boardpart != ""} { ## set_property "board_part" $boardpart [current_project] ## } ## set report_dir $projdir/reports ## set results_dir $projdir/results ## if ![file exists $report_dir] {file mkdir $report_dir} ## if ![file exists $results_dir] {file mkdir $results_dir} ## set other_repos [get_property ip_repo_paths [current_project]] ## set_property ip_repo_paths "$ip_repos $other_repos" [current_project] ## update_ip_catalog INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/promach/Documents/Grive/Personal/Digital/Parallella/parallella-riscv/parallella/fpga/parallella_base'. INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/promach/Documents/Grive/Personal/Digital/Parallella/parallella-riscv/parallella/fpga/riscv_rv64'. INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2017.1/data/ip'. ## create_bd_design "system" Wrote : ## source ./system_bd.tcl ### set scripts_vivado_version 2017.1 ### set current_vivado_version [version -short] ### if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { ### puts "" ### puts "ERROR: This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script." ### ### return 1 ### } ### if { [get_projects -quiet] eq "" } { ### puts "ERROR: Please open or create a project!" ### return 1 ### } ### set design_name system ### set errMsg "" ### set nRet 0 ### set cur_design [current_bd_design -quiet] ### set list_cells [get_bd_cells -quiet] ### if { ${design_name} eq "" } { ### # USE CASES: ### # 1) Design_name not set ### ### set errMsg "ERROR: Please set the variable to a non-empty value." ### set nRet 1 ### ### } elseif { ${cur_design} ne "" && ${list_cells} eq "" } { ### # USE CASES: ### # 2): Current design opened AND is empty AND names same. ### # 3): Current design opened AND is empty AND names diff; design_name NOT in project. ### # 4): Current design opened AND is empty AND names diff; design_name exists in project. ### ### if { $cur_design ne $design_name } { ### puts "INFO: Changing value of from <$design_name> to <$cur_design> since current design is empty." ### set design_name [get_property NAME $cur_design] ### } ### puts "INFO: Constructing design in IPI design <$cur_design>..." ### ### } elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { ### # USE CASES: ### # 5) Current design opened AND has components AND same names. ### ### set errMsg "ERROR: Design <$design_name> already exists in your project, please set the variable to another value." ### set nRet 1 ### } elseif { [get_files -quiet ${design_name}.bd] ne "" } { ### # USE CASES: ### # 6) Current opened design, has components, but diff names, design_name exists in project. ### # 7) No opened design, design_name exists in project. ### ### set errMsg "ERROR: Design <$design_name> already exists in your project, please set the variable to another value." ### set nRet 2 ### ### } else { ### # USE CASES: ### # 8) No opened design, design_name not in project. ### # 9) Current opened design, has components, but diff names, design_name not in project. ### ### puts "INFO: Currently there is no design <$design_name> in project, so creating one..." ### ### create_bd_design $design_name ### ### puts "INFO: Making design <$design_name> as current_bd_design." ### current_bd_design $design_name ### ### } INFO: Constructing design in IPI design ... ### puts "INFO: Currently the variable is equal to \"$design_name\"." INFO: Currently the variable is equal to "system". ### if { $nRet != 0 } { ### puts $errMsg ### return $nRet ### } ### proc create_root_design { parentCell } { ### ### global rv64_clk_jitter ### global rv64_clk_phase_error ### global rv64_clk_request_freq ### global rv64_clk_multiplier ### global rv64_clk_divider1 ### global rv64_clk_divider2 ### ### global parallella_gpio_ports ### ### set parallella_gpio_last [expr {$parallella_gpio_ports - 1}] ### ### if { $parentCell eq "" } { ### set parentCell [get_bd_cells /] ### } ### ### # Get object for parentCell ### set parentObj [get_bd_cells $parentCell] ### if { $parentObj == "" } { ### puts "ERROR: Unable to find parent cell <$parentCell>!" ### return ### } ### ### # Make sure parentObj is hier blk ### set parentType [get_property TYPE $parentObj] ### if { $parentType ne "hier" } { ### puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be ." ### return ### } ### ### # Save current instance; Restore later ### set oldCurInst [current_bd_instance .] ### ### # Set parent object as current ### current_bd_instance $parentObj ### ### ### # Create interface ports ### set DDR [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR ] ### set FIXED_IO [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 FIXED_IO ] ### ### # Create ports ### set cclk_n [ create_bd_port -dir O cclk_n ] ### set cclk_p [ create_bd_port -dir O cclk_p ] ### set chip_nreset [ create_bd_port -dir O chip_nreset ] ### set gpio_n [ create_bd_port -dir IO -from $parallella_gpio_last -to 0 gpio_n ] ### set gpio_p [ create_bd_port -dir IO -from $parallella_gpio_last -to 0 gpio_p ] ### set hdmi_clk [ create_bd_port -dir O hdmi_clk ] ### set hdmi_d [ create_bd_port -dir O -from 23 -to 8 hdmi_d ] ### set hdmi_de [ create_bd_port -dir O hdmi_de ] ### set hdmi_hsync [ create_bd_port -dir O hdmi_hsync ] ### set hdmi_int [ create_bd_port -dir I hdmi_int ] ### set hdmi_spdif [ create_bd_port -dir O hdmi_spdif ] ### set hdmi_vsync [ create_bd_port -dir O hdmi_vsync ] ### set i2c_scl [ create_bd_port -dir IO i2c_scl ] ### set i2c_sda [ create_bd_port -dir IO i2c_sda ] ### set rxi_data_n [ create_bd_port -dir I -from 7 -to 0 rxi_data_n ] ### set rxi_data_p [ create_bd_port -dir I -from 7 -to 0 rxi_data_p ] ### set rxi_frame_n [ create_bd_port -dir I rxi_frame_n ] ### set rxi_frame_p [ create_bd_port -dir I rxi_frame_p ] ### set rxi_lclk_n [ create_bd_port -dir I rxi_lclk_n ] ### set rxi_lclk_p [ create_bd_port -dir I rxi_lclk_p ] ### set rxo_rd_wait_n [ create_bd_port -dir O rxo_rd_wait_n ] ### set rxo_rd_wait_p [ create_bd_port -dir O rxo_rd_wait_p ] ### set rxo_wr_wait_n [ create_bd_port -dir O rxo_wr_wait_n ] ### set rxo_wr_wait_p [ create_bd_port -dir O rxo_wr_wait_p ] ### set txi_rd_wait_n [ create_bd_port -dir I txi_rd_wait_n ] ### set txi_rd_wait_p [ create_bd_port -dir I txi_rd_wait_p ] ### set txi_wr_wait_n [ create_bd_port -dir I txi_wr_wait_n ] ### set txi_wr_wait_p [ create_bd_port -dir I txi_wr_wait_p ] ### set txo_data_n [ create_bd_port -dir O -from 7 -to 0 txo_data_n ] ### set txo_data_p [ create_bd_port -dir O -from 7 -to 0 txo_data_p ] ### set txo_frame_n [ create_bd_port -dir O txo_frame_n ] ### set txo_frame_p [ create_bd_port -dir O txo_frame_p ] ### set txo_lclk_n [ create_bd_port -dir O txo_lclk_n ] ### set txo_lclk_p [ create_bd_port -dir O txo_lclk_p ] ### ### # Create instance: RISCV_Rocket_Core_RV64G_0, and set properties ### set RISCV_Rocket_Core_RV64_0 [ create_bd_cell -type ip -vlnv www.parallella.org:user:RISCV_Rocket_Core_RV64: RISCV_Rocket_Core_RV64_0 ] ### ### # Create instance: axi_mem_intercon, and set properties ### set axi_mem_intercon [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect: axi_mem_intercon ] ### set_property -dict [ list \ ### CONFIG.NUM_MI {1} \ ### ] $axi_mem_intercon ### ### # Create instance: axi_mem_intercon_PS_master, and set properties ### set axi_mem_intercon_PS_master [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect: axi_mem_intercon_PS_master ] ### set_property -dict [ list \ ### CONFIG.NUM_MI {1} \ ### ] $axi_mem_intercon_PS_master ### ### # Create instance: axi_mem_intercon_PS_slave, and set properties ### set axi_mem_intercon_PS_slave [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect: axi_mem_intercon_PS_slave ] ### set_property -dict [ list \ ### CONFIG.NUM_MI {1} \ ### ] $axi_mem_intercon_PS_slave ### ### # Create instance: rv64_mmcm_0, and set properties ### set rv64_mmcm_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz: rv64_mmcm_0 ] ### set_property -dict [ list \ ### CONFIG.CLKOUT1_DRIVES {BUFG} \ ### CONFIG.CLKOUT1_JITTER $rv64_clk_jitter \ ### CONFIG.CLKOUT1_PHASE_ERROR $rv64_clk_phase_error \ ### CONFIG.CLKOUT1_REQUESTED_OUT_FREQ $rv64_clk_request_freq \ ### CONFIG.FEEDBACK_SOURCE {FDBK_AUTO} \ ### CONFIG.MMCM_CLKFBOUT_MULT_F $rv64_clk_multiplier \ ### CONFIG.MMCM_CLKOUT0_DIVIDE_F $rv64_clk_divider1 \ ### CONFIG.MMCM_DIVCLK_DIVIDE $rv64_clk_divider2 \ ### CONFIG.PRIM_SOURCE {No_buffer} \ ### CONFIG.RESET_PORT {resetn} \ ### CONFIG.RESET_TYPE {ACTIVE_LOW} \ ### ] $rv64_mmcm_0 ### ### # Create instance: parallella_base_0, and set properties ### set parallella_base_0 [ create_bd_cell -type ip -vlnv www.parallella.org:user:parallella_base: parallella_base_0 ] ### set_property -dict [ list \ ### CONFIG.NGPIO $parallella_gpio_ports \ ### ] $parallella_base_0 ### ### # Create instance: proc_sys_reset_0, and set properties ### set proc_sys_reset_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset: proc_sys_reset_0 ] ### ### # Create instance: processing_system7_0, and set properties ### set processing_system7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7: processing_system7_0 ] ### set_property -dict [ list \ ### CONFIG.PCW_CORE0_FIQ_INTR {0} \ ### CONFIG.PCW_ENET0_ENET0_IO {MIO 16 .. 27} \ ### CONFIG.PCW_ENET0_GRP_MDIO_ENABLE {1} \ ### CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {1} \ ### CONFIG.PCW_ENET1_PERIPHERAL_ENABLE {0} \ ### CONFIG.PCW_EN_CLK3_PORT {1} \ ### CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100} \ ### CONFIG.PCW_FPGA3_PERIPHERAL_FREQMHZ {100} \ ### CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1} \ ### CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1} \ ### CONFIG.PCW_GPIO_MIO_GPIO_IO {MIO} \ ### CONFIG.PCW_I2C0_I2C0_IO {EMIO} \ ### CONFIG.PCW_I2C0_PERIPHERAL_ENABLE {1} \ ### CONFIG.PCW_I2C0_RESET_ENABLE {0} \ ### CONFIG.PCW_IRQ_F2P_INTR {1} \ ### CONFIG.PCW_IRQ_F2P_MODE {DIRECT} \ ### CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V} \ ### CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE {1} \ ### CONFIG.PCW_QSPI_PERIPHERAL_ENABLE {1} \ ### CONFIG.PCW_SD1_PERIPHERAL_ENABLE {1} \ ### CONFIG.PCW_SD1_SD1_IO {MIO 10 .. 15} \ ### CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ {50} \ ### CONFIG.PCW_UART1_PERIPHERAL_ENABLE {1} \ ### CONFIG.PCW_UART1_UART1_IO {MIO 8 .. 9} \ ### CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.434} \ ### CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.398} \ ### CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2 {0.410} \ ### CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3 {0.455} \ ### CONFIG.PCW_UIPARAM_DDR_CL {9} \ ### CONFIG.PCW_UIPARAM_DDR_CWL {9} \ ### CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY {8192 MBits} \ ### CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {0.315} \ ### CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {0.391} \ ### CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 {0.374} \ ### CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 {0.271} \ ### CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH {32 Bits} \ ### CONFIG.PCW_UIPARAM_DDR_FREQ_MHZ {400.00} \ ### CONFIG.PCW_UIPARAM_DDR_PARTNO {Custom} \ ### CONFIG.PCW_UIPARAM_DDR_T_FAW {50} \ ### CONFIG.PCW_UIPARAM_DDR_T_RAS_MIN {40} \ ### CONFIG.PCW_UIPARAM_DDR_T_RC {60} \ ### CONFIG.PCW_UIPARAM_DDR_T_RCD {9} \ ### CONFIG.PCW_UIPARAM_DDR_T_RP {9} \ ### CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF {1} \ ### CONFIG.PCW_USB0_PERIPHERAL_ENABLE {1} \ ### CONFIG.PCW_USB0_RESET_ENABLE {0} \ ### CONFIG.PCW_USB1_PERIPHERAL_ENABLE {1} \ ### CONFIG.PCW_USE_FABRIC_INTERRUPT {1} \ ### CONFIG.PCW_USE_M_AXI_GP0 {1} \ ### CONFIG.PCW_USE_M_AXI_GP1 {1} \ ### CONFIG.PCW_USE_S_AXI_HP0 {1} \ ### CONFIG.PCW_USE_S_AXI_HP1 {1} \ ### ] $processing_system7_0 ### ### # Create instance: processing_system7_0_axi_periph, and set properties ### set processing_system7_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect: processing_system7_0_axi_periph ] ### set_property -dict [ list \ ### CONFIG.NUM_MI {1} \ ### ] $processing_system7_0_axi_periph ### ### # Create instance: rv64_sys_reset_0, and set properties ### set rv64_sys_reset_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset: rv64_sys_reset_0 ] ### ### # Create instance: sys_concat_intc, and set properties ### set sys_concat_intc [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat: sys_concat_intc ] ### set_property -dict [ list \ ### CONFIG.NUM_PORTS {16} \ ### ] $sys_concat_intc ### ### # Create interface connections ### connect_bd_intf_net -intf_net RISCV_Rocket_Core_RV64_0_M_AXI [get_bd_intf_pins RISCV_Rocket_Core_RV64_0/m_axi] [get_bd_intf_pins axi_mem_intercon_PS_slave/S00_AXI] ### connect_bd_intf_net -intf_net axi_mem_intercon_1_M00_AXI [get_bd_intf_pins axi_mem_intercon_PS_slave/M00_AXI] [get_bd_intf_pins processing_system7_0/S_AXI_HP0] ### connect_bd_intf_net -intf_net axi_mem_intercon_M00_AXI [get_bd_intf_pins axi_mem_intercon/M00_AXI] [get_bd_intf_pins processing_system7_0/S_AXI_HP1] ### connect_bd_intf_net -intf_net axi_mem_intercon_RV64_M00_AXI [get_bd_intf_pins RISCV_Rocket_Core_RV64_0/s_axi] [get_bd_intf_pins axi_mem_intercon_PS_master/M00_AXI] ### connect_bd_intf_net -intf_net parallella_base_0_m_axi [get_bd_intf_pins axi_mem_intercon/S00_AXI] [get_bd_intf_pins parallella_base_0/m_axi] ### connect_bd_intf_net -intf_net processing_system7_0_DDR [get_bd_intf_ports DDR] [get_bd_intf_pins processing_system7_0/DDR] ### connect_bd_intf_net -intf_net processing_system7_0_FIXED_IO [get_bd_intf_ports FIXED_IO] [get_bd_intf_pins processing_system7_0/FIXED_IO] ### connect_bd_intf_net -intf_net processing_system7_0_M_AXI_GP0 [get_bd_intf_pins axi_mem_intercon_PS_master/S00_AXI] [get_bd_intf_pins processing_system7_0/M_AXI_GP0] ### connect_bd_intf_net -intf_net processing_system7_0_M_AXI_GP1 [get_bd_intf_pins processing_system7_0/M_AXI_GP1] [get_bd_intf_pins processing_system7_0_axi_periph/S00_AXI] ### connect_bd_intf_net -intf_net processing_system7_0_axi_periph_M00_AXI [get_bd_intf_pins parallella_base_0/s_axi] [get_bd_intf_pins processing_system7_0_axi_periph/M00_AXI] ### ### # Create port connections ### connect_bd_net -net Net [get_bd_ports gpio_n] [get_bd_pins parallella_base_0/gpio_n] ### connect_bd_net -net Net1 [get_bd_ports gpio_p] [get_bd_pins parallella_base_0/gpio_p] ### connect_bd_net -net Net2 [get_bd_ports i2c_scl] [get_bd_pins parallella_base_0/i2c_scl] ### connect_bd_net -net Net3 [get_bd_ports i2c_sda] [get_bd_pins parallella_base_0/i2c_sda] ### connect_bd_net -net clk_wiz_0_clk_out1 [get_bd_pins RISCV_Rocket_Core_RV64_0/m_axi_aclk] [get_bd_pins RISCV_Rocket_Core_RV64_0/s_axi_aclk] [get_bd_pins axi_mem_intercon_PS_master/ACLK] [get_bd_pins axi_mem_intercon_PS_master/M00_ACLK] [get_bd_pins axi_mem_intercon_PS_master/S00_ACLK] [get_bd_pins axi_mem_intercon_PS_slave/ACLK] [get_bd_pins axi_mem_intercon_PS_slave/M00_ACLK] [get_bd_pins axi_mem_intercon_PS_slave/S00_ACLK] [get_bd_pins rv64_mmcm_0/clk_out1] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins processing_system7_0/S_AXI_HP0_ACLK] [get_bd_pins rv64_sys_reset_0/slowest_sync_clk] ### connect_bd_net -net clk_wiz_0_locked [get_bd_pins rv64_mmcm_0/locked] [get_bd_pins rv64_sys_reset_0/dcm_locked] ### connect_bd_net -net parallella_base_0_cclk_n [get_bd_ports cclk_n] [get_bd_pins parallella_base_0/cclk_n] ### connect_bd_net -net parallella_base_0_cclk_p [get_bd_ports cclk_p] [get_bd_pins parallella_base_0/cclk_p] ### connect_bd_net -net parallella_base_0_chip_resetb [get_bd_ports chip_nreset] [get_bd_pins parallella_base_0/chip_nreset] ### connect_bd_net -net parallella_base_0_constant_zero [get_bd_pins parallella_base_0/constant_zero] [get_bd_pins sys_concat_intc/In0] [get_bd_pins sys_concat_intc/In1] [get_bd_pins sys_concat_intc/In2] [get_bd_pins sys_concat_intc/In3] [get_bd_pins sys_concat_intc/In4] [get_bd_pins sys_concat_intc/In5] [get_bd_pins sys_concat_intc/In6] [get_bd_pins sys_concat_intc/In7] [get_bd_pins sys_concat_intc/In8] [get_bd_pins sys_concat_intc/In9] [get_bd_pins sys_concat_intc/In10] [get_bd_pins sys_concat_intc/In12] [get_bd_pins sys_concat_intc/In13] [get_bd_pins sys_concat_intc/In14] [get_bd_pins sys_concat_intc/In15] ### connect_bd_net -net parallella_base_0_i2c_scl_i [get_bd_pins parallella_base_0/i2c_scl_i] [get_bd_pins processing_system7_0/I2C0_SCL_I] ### connect_bd_net -net parallella_base_0_i2c_sda_i [get_bd_pins parallella_base_0/i2c_sda_i] [get_bd_pins processing_system7_0/I2C0_SDA_I] ### connect_bd_net -net parallella_base_0_mailbox_irq [get_bd_pins parallella_base_0/mailbox_irq] [get_bd_pins sys_concat_intc/In11] ### connect_bd_net -net parallella_base_0_ps_gpio_i [get_bd_pins parallella_base_0/ps_gpio_i] [get_bd_pins processing_system7_0/GPIO_I] ### connect_bd_net -net parallella_base_0_rxo_rd_wait_n [get_bd_ports rxo_rd_wait_n] [get_bd_pins parallella_base_0/rxo_rd_wait_n] ### connect_bd_net -net parallella_base_0_rxo_rd_wait_p [get_bd_ports rxo_rd_wait_p] [get_bd_pins parallella_base_0/rxo_rd_wait_p] ### connect_bd_net -net parallella_base_0_rxo_wr_wait_n [get_bd_ports rxo_wr_wait_n] [get_bd_pins parallella_base_0/rxo_wr_wait_n] ### connect_bd_net -net parallella_base_0_rxo_wr_wait_p [get_bd_ports rxo_wr_wait_p] [get_bd_pins parallella_base_0/rxo_wr_wait_p] ### connect_bd_net -net parallella_base_0_txo_data_n [get_bd_ports txo_data_n] [get_bd_pins parallella_base_0/txo_data_n] ### connect_bd_net -net parallella_base_0_txo_data_p [get_bd_ports txo_data_p] [get_bd_pins parallella_base_0/txo_data_p] ### connect_bd_net -net parallella_base_0_txo_frame_n [get_bd_ports txo_frame_n] [get_bd_pins parallella_base_0/txo_frame_n] ### connect_bd_net -net parallella_base_0_txo_frame_p [get_bd_ports txo_frame_p] [get_bd_pins parallella_base_0/txo_frame_p] ### connect_bd_net -net parallella_base_0_txo_lclk_n [get_bd_ports txo_lclk_n] [get_bd_pins parallella_base_0/txo_lclk_n] ### connect_bd_net -net parallella_base_0_txo_lclk_p [get_bd_ports txo_lclk_p] [get_bd_pins parallella_base_0/txo_lclk_p] ### connect_bd_net -net proc_sys_reset_0_interconnect_aresetn [get_bd_pins axi_mem_intercon/ARESETN] [get_bd_pins proc_sys_reset_0/interconnect_aresetn] [get_bd_pins processing_system7_0_axi_periph/ARESETN] ### connect_bd_net -net proc_sys_reset_0_peripheral_aresetn [get_bd_pins axi_mem_intercon/M00_ARESETN] [get_bd_pins axi_mem_intercon/S00_ARESETN] [get_bd_pins parallella_base_0/m_axi_aresetn] [get_bd_pins parallella_base_0/s_axi_aresetn] [get_bd_pins parallella_base_0/sys_nreset] [get_bd_pins proc_sys_reset_0/peripheral_aresetn] [get_bd_pins processing_system7_0_axi_periph/M00_ARESETN] [get_bd_pins processing_system7_0_axi_periph/S00_ARESETN] ### connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_pins axi_mem_intercon/ACLK] [get_bd_pins axi_mem_intercon/M00_ACLK] [get_bd_pins axi_mem_intercon/S00_ACLK] [get_bd_pins parallella_base_0/sys_clk] [get_bd_pins proc_sys_reset_0/slowest_sync_clk] [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP1_ACLK] [get_bd_pins processing_system7_0/S_AXI_HP1_ACLK] [get_bd_pins processing_system7_0_axi_periph/ACLK] [get_bd_pins processing_system7_0_axi_periph/M00_ACLK] [get_bd_pins processing_system7_0_axi_periph/S00_ACLK] ### connect_bd_net -net processing_system7_0_FCLK_CLK3 [get_bd_pins rv64_mmcm_0/clk_in1] [get_bd_pins processing_system7_0/FCLK_CLK3] ### connect_bd_net -net processing_system7_0_FCLK_RESET0_N [get_bd_pins rv64_mmcm_0/resetn] [get_bd_pins proc_sys_reset_0/ext_reset_in] [get_bd_pins processing_system7_0/FCLK_RESET0_N] [get_bd_pins rv64_sys_reset_0/ext_reset_in] ### connect_bd_net -net processing_system7_0_GPIO_O [get_bd_pins parallella_base_0/ps_gpio_o] [get_bd_pins processing_system7_0/GPIO_O] ### connect_bd_net -net processing_system7_0_GPIO_T [get_bd_pins parallella_base_0/ps_gpio_t] [get_bd_pins processing_system7_0/GPIO_T] ### connect_bd_net -net processing_system7_0_I2C0_SCL_O [get_bd_pins parallella_base_0/i2c_scl_o] [get_bd_pins processing_system7_0/I2C0_SCL_O] ### connect_bd_net -net processing_system7_0_I2C0_SCL_T [get_bd_pins parallella_base_0/i2c_scl_t] [get_bd_pins processing_system7_0/I2C0_SCL_T] ### connect_bd_net -net processing_system7_0_I2C0_SDA_O [get_bd_pins parallella_base_0/i2c_sda_o] [get_bd_pins processing_system7_0/I2C0_SDA_O] ### connect_bd_net -net processing_system7_0_I2C0_SDA_T [get_bd_pins parallella_base_0/i2c_sda_t] [get_bd_pins processing_system7_0/I2C0_SDA_T] ### connect_bd_net -net rv64_sys_reset_0_interconnect_aresetn [get_bd_pins axi_mem_intercon_PS_master/ARESETN] [get_bd_pins axi_mem_intercon_PS_slave/ARESETN] [get_bd_pins rv64_sys_reset_0/interconnect_aresetn] ### connect_bd_net -net rv64_sys_reset_0_peripheral_aresetn [get_bd_pins RISCV_Rocket_Core_RV64_0/m_axi_aresetn] [get_bd_pins RISCV_Rocket_Core_RV64_0/s_axi_aresetn] [get_bd_pins axi_mem_intercon_PS_master/M00_ARESETN] [get_bd_pins axi_mem_intercon_PS_master/S00_ARESETN] [get_bd_pins axi_mem_intercon_PS_slave/M00_ARESETN] [get_bd_pins axi_mem_intercon_PS_slave/S00_ARESETN] [get_bd_pins rv64_sys_reset_0/peripheral_aresetn] ### connect_bd_net -net rxi_data_n_1 [get_bd_ports rxi_data_n] [get_bd_pins parallella_base_0/rxi_data_n] ### connect_bd_net -net rxi_data_p_1 [get_bd_ports rxi_data_p] [get_bd_pins parallella_base_0/rxi_data_p] ### connect_bd_net -net rxi_frame_n_1 [get_bd_ports rxi_frame_n] [get_bd_pins parallella_base_0/rxi_frame_n] ### connect_bd_net -net rxi_frame_p_1 [get_bd_ports rxi_frame_p] [get_bd_pins parallella_base_0/rxi_frame_p] ### connect_bd_net -net rxi_lclk_n_1 [get_bd_ports rxi_lclk_n] [get_bd_pins parallella_base_0/rxi_lclk_n] ### connect_bd_net -net rxi_lclk_p_1 [get_bd_ports rxi_lclk_p] [get_bd_pins parallella_base_0/rxi_lclk_p] ### connect_bd_net -net sys_concat_intc_dout [get_bd_pins processing_system7_0/IRQ_F2P] [get_bd_pins sys_concat_intc/dout] ### connect_bd_net -net txi_rd_wait_n_1 [get_bd_ports txi_rd_wait_n] [get_bd_pins parallella_base_0/txi_rd_wait_n] ### connect_bd_net -net txi_rd_wait_p_1 [get_bd_ports txi_rd_wait_p] [get_bd_pins parallella_base_0/txi_rd_wait_p] ### connect_bd_net -net txi_wr_wait_n_1 [get_bd_ports txi_wr_wait_n] [get_bd_pins parallella_base_0/txi_wr_wait_n] ### connect_bd_net -net txi_wr_wait_p_1 [get_bd_ports txi_wr_wait_p] [get_bd_pins parallella_base_0/txi_wr_wait_p] ### ### # Create address segments ### create_bd_addr_seg -range 0x40000000 -offset 0x0 [get_bd_addr_spaces RISCV_Rocket_Core_RV64_0/m_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP0/HP0_DDR_LOWOCM] SEG_processing_system7_0_HP0_DDR_LOWOCM ### create_bd_addr_seg -range 0x40000000 -offset 0x0 [get_bd_addr_spaces parallella_base_0/m_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_processing_system7_0_HP1_DDR_LOWOCM ### create_bd_addr_seg -range 0x1000 -offset 0x43C00000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs RISCV_Rocket_Core_RV64_0/s_axi/axi_lite] SEG_RISCV_Rocket_Core_RV64_0_axi_lite ### create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs parallella_base_0/s_axi/axi_lite] SEG_parallella_base_0_axi_lite ### ### ### # Restore current instance ### current_bd_instance $oldCurInst ### ### save_bd_design ### } ### create_root_design "" WARNING: [BD 41-1753] The name 'axi_mem_intercon_PS_master' you have specified is long. The Windows OS has path length limitations. It is recommended you use shorter names(less than 25 characters) to reduce the likelihood of issues when/if running on windows OS. WARNING: [BD 41-1753] The name 'processing_system7_0_axi_periph' you have specified is long. The Windows OS has path length limitations. It is recommended you use shorter names(less than 25 characters) to reduce the likelihood of issues when/if running on windows OS. WARNING: [BD 41-1306] The connection to interface pin /processing_system7_0/I2C0_SCL_I is being overridden by the user. This pin will not be connected as a part of interface connection IIC_0 WARNING: [BD 41-1306] The connection to interface pin /processing_system7_0/I2C0_SDA_I is being overridden by the user. This pin will not be connected as a part of interface connection IIC_0 WARNING: [BD 41-1306] The connection to interface pin /processing_system7_0/GPIO_I is being overridden by the user. This pin will not be connected as a part of interface connection GPIO_0 WARNING: [BD 41-1731] Type mismatch between connected pins: /parallella_base_0/sys_nreset(undef) and /proc_sys_reset_0/peripheral_aresetn(rst) WARNING: [BD 41-1306] The connection to interface pin /processing_system7_0/GPIO_O is being overridden by the user. This pin will not be connected as a part of interface connection GPIO_0 WARNING: [BD 41-1306] The connection to interface pin /processing_system7_0/GPIO_T is being overridden by the user. This pin will not be connected as a part of interface connection GPIO_0 WARNING: [BD 41-1306] The connection to interface pin /processing_system7_0/I2C0_SCL_O is being overridden by the user. This pin will not be connected as a part of interface connection IIC_0 WARNING: [BD 41-1306] The connection to interface pin /processing_system7_0/I2C0_SCL_T is being overridden by the user. This pin will not be connected as a part of interface connection IIC_0 WARNING: [BD 41-1306] The connection to interface pin /processing_system7_0/I2C0_SDA_O is being overridden by the user. This pin will not be connected as a part of interface connection IIC_0 WARNING: [BD 41-1306] The connection to interface pin /processing_system7_0/I2C0_SDA_T is being overridden by the user. This pin will not be connected as a part of interface connection IIC_0 Wrote : ## make_wrapper -files [get_files $projdir/${design}.srcs/sources_1/bd/system/system.bd] -top Wrote : WARNING: [BD 41-235] Width mismatch when connecting pin: '/axi_mem_intercon_PS_slave/s00_couplers/auto_pc/m_axi_bid'(5) to net 'auto_pc_to_s00_couplers_BID'(6) - Only lower order bits will be connected. WARNING: [BD 41-235] Width mismatch when connecting pin: '/axi_mem_intercon_PS_slave/s00_couplers/auto_pc/m_axi_rid'(5) to net 'auto_pc_to_s00_couplers_RID'(6) - Only lower order bits will be connected. WARNING: [BD 41-235] Width mismatch when connecting pin: '/processing_system7_0/S_AXI_HP0_AWID'(6) to net 'axi_mem_intercon_1_M00_AXI_AWID'(5) - Only lower order bits will be connected. WARNING: [BD 41-235] Width mismatch when connecting pin: '/processing_system7_0/S_AXI_HP0_WID'(6) to net 'axi_mem_intercon_1_M00_AXI_WID'(5) - Only lower order bits will be connected. WARNING: [BD 41-235] Width mismatch when connecting pin: '/processing_system7_0/S_AXI_HP0_ARID'(6) to net 'axi_mem_intercon_1_M00_AXI_ARID'(5) - Only lower order bits will be connected. Verilog Output written to : /home/promach/Documents/Grive/Personal/Digital/Parallella/parallella-riscv/parallella/fpga/parallella_riscv/system.srcs/sources_1/bd/system/hdl/system.v Verilog Output written to : /home/promach/Documents/Grive/Personal/Digital/Parallella/parallella-riscv/parallella/fpga/parallella_riscv/system.srcs/sources_1/bd/system/hdl/system_wrapper.v ## if {[string equal [get_filesets -quiet sources_1] ""]} { ## create_fileset -srcset sources_1 ## } ## set top_wrapper $projdir/${design}.srcs/sources_1/bd/system/hdl/system_wrapper.v ## add_files -norecurse -fileset [get_filesets sources_1] $top_wrapper ## if {[llength $hdl_files] != 0} { ## add_files -norecurse -fileset [get_filesets sources_1] $hdl_files ## } ## if {[string equal [get_filesets -quiet constrs_1] ""]} { ## create_fileset -constrset constrs_1 ## } ## if {[llength $constraints_files] != 0} { ## add_files -norecurse -fileset [get_filesets constrs_1] $constraints_files ## } # source ../../scripts/vivado/system_build.tcl ## validate_bd_design INFO: [BD 5-320] Validate design is not run, since the design is already validated. ## write_bd_tcl -force ./system_bd_new.tcl INFO: [BD 5-148] Tcl file written out . ## make_wrapper -files [get_files $projdir/${design}.srcs/sources_1/bd/system/system.bd] -top INFO: [BD 41-1662] The design 'system.bd' is already validated. Therefore parameter propagation will not be re-run. WARNING: [BD 41-235] Width mismatch when connecting pin: '/axi_mem_intercon_PS_slave/s00_couplers/auto_pc/m_axi_bid'(5) to net 'auto_pc_to_s00_couplers_BID'(6) - Only lower order bits will be connected. WARNING: [BD 41-235] Width mismatch when connecting pin: '/axi_mem_intercon_PS_slave/s00_couplers/auto_pc/m_axi_rid'(5) to net 'auto_pc_to_s00_couplers_RID'(6) - Only lower order bits will be connected. WARNING: [BD 41-235] Width mismatch when connecting pin: '/processing_system7_0/S_AXI_HP0_AWID'(6) to net 'axi_mem_intercon_1_M00_AXI_AWID'(5) - Only lower order bits will be connected. WARNING: [BD 41-235] Width mismatch when connecting pin: '/processing_system7_0/S_AXI_HP0_WID'(6) to net 'axi_mem_intercon_1_M00_AXI_WID'(5) - Only lower order bits will be connected. WARNING: [BD 41-235] Width mismatch when connecting pin: '/processing_system7_0/S_AXI_HP0_ARID'(6) to net 'axi_mem_intercon_1_M00_AXI_ARID'(5) - Only lower order bits will be connected. Verilog Output written to : /home/promach/Documents/Grive/Personal/Digital/Parallella/parallella-riscv/parallella/fpga/parallella_riscv/system.srcs/sources_1/bd/system/hdl/system.v Verilog Output written to : /home/promach/Documents/Grive/Personal/Digital/Parallella/parallella-riscv/parallella/fpga/parallella_riscv/system.srcs/sources_1/bd/system/hdl/system_wrapper.v ## remove_files -fileset sources_1 $projdir/${design}.srcs/sources_1/bd/system/hdl/system_wrapper.v ## add_files -fileset sources_1 -norecurse $projdir/${design}.srcs/sources_1/bd/system/hdl/system_wrapper.v ## launch_runs synth_1 INFO: [BD 41-1662] The design 'system.bd' is already validated. Therefore parameter propagation will not be re-run. WARNING: [BD 41-235] Width mismatch when connecting pin: '/axi_mem_intercon_PS_slave/s00_couplers/auto_pc/m_axi_bid'(5) to net 'auto_pc_to_s00_couplers_BID'(6) - Only lower order bits will be connected. WARNING: [BD 41-235] Width mismatch when connecting pin: '/axi_mem_intercon_PS_slave/s00_couplers/auto_pc/m_axi_rid'(5) to net 'auto_pc_to_s00_couplers_RID'(6) - Only lower order bits will be connected. WARNING: [BD 41-235] Width mismatch when connecting pin: '/processing_system7_0/S_AXI_HP0_AWID'(6) to net 'axi_mem_intercon_1_M00_AXI_AWID'(5) - Only lower order bits will be connected. WARNING: [BD 41-235] Width mismatch when connecting pin: '/processing_system7_0/S_AXI_HP0_WID'(6) to net 'axi_mem_intercon_1_M00_AXI_WID'(5) - Only lower order bits will be connected. WARNING: [BD 41-235] Width mismatch when connecting pin: '/processing_system7_0/S_AXI_HP0_ARID'(6) to net 'axi_mem_intercon_1_M00_AXI_ARID'(5) - Only lower order bits will be connected. Verilog Output written to : /home/promach/Documents/Grive/Personal/Digital/Parallella/parallella-riscv/parallella/fpga/parallella_riscv/system.srcs/sources_1/bd/system/hdl/system.v Verilog Output written to : /home/promach/Documents/Grive/Personal/Digital/Parallella/parallella-riscv/parallella/fpga/parallella_riscv/system.srcs/sources_1/bd/system/hdl/system_wrapper.v INFO: [BD 41-1029] Generation completed for the IP Integrator block RISCV_Rocket_Core_RV64_0 . INFO: [BD 41-1029] Generation completed for the IP Integrator block rv64_mmcm_0 . INFO: [BD 41-1029] Generation completed for the IP Integrator block parallella_base_0 . INFO: [BD 41-1029] Generation completed for the IP Integrator block proc_sys_reset_0 . INFO: [BD 41-1029] Generation completed for the IP Integrator block processing_system7_0 . INFO: [BD 41-1029] Generation completed for the IP Integrator block rv64_sys_reset_0 . INFO: [BD 41-1029] Generation completed for the IP Integrator block sys_concat_intc . WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/promach/Documents/Grive/Personal/Digital/Parallella/parallella-riscv/parallella/fpga/parallella_riscv/system.srcs/sources_1/bd/system/ip/system_auto_pc_3/system_auto_pc_3_ooc.xdc' INFO: [BD 41-1029] Generation completed for the IP Integrator block processing_system7_0_axi_periph/s00_couplers/auto_pc . WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/promach/Documents/Grive/Personal/Digital/Parallella/parallella-riscv/parallella/fpga/parallella_riscv/system.srcs/sources_1/bd/system/ip/system_auto_pc_2/system_auto_pc_2_ooc.xdc' INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_mem_intercon_PS_slave/s00_couplers/auto_pc . WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/promach/Documents/Grive/Personal/Digital/Parallella/parallella-riscv/parallella/fpga/parallella_riscv/system.srcs/sources_1/bd/system/ip/system_auto_pc_1/system_auto_pc_1_ooc.xdc' INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_mem_intercon_PS_master/s00_couplers/auto_pc . WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/promach/Documents/Grive/Personal/Digital/Parallella/parallella-riscv/parallella/fpga/parallella_riscv/system.srcs/sources_1/bd/system/ip/system_auto_pc_0/system_auto_pc_0_ooc.xdc' INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_mem_intercon/s00_couplers/auto_pc . Exporting to file /home/promach/Documents/Grive/Personal/Digital/Parallella/parallella-riscv/parallella/fpga/parallella_riscv/system.srcs/sources_1/bd/system/hw_handoff/system.hwh Generated Block Design Tcl file /home/promach/Documents/Grive/Personal/Digital/Parallella/parallella-riscv/parallella/fpga/parallella_riscv/system.srcs/sources_1/bd/system/hw_handoff/system_bd.tcl Generated Hardware Definition File /home/promach/Documents/Grive/Personal/Digital/Parallella/parallella-riscv/parallella/fpga/parallella_riscv/system.srcs/sources_1/bd/system/hdl/system.hwdef [Thu May 25 14:14:43 2017] Launched system_RISCV_Rocket_Core_RV64_0_0_synth_1, system_auto_pc_3_synth_1, system_auto_pc_2_synth_1, system_auto_pc_1_synth_1, system_auto_pc_0_synth_1, system_sys_concat_intc_0_synth_1, system_processing_system7_0_0_synth_1, system_rv64_sys_reset_0_0_synth_1, system_proc_sys_reset_0_0_synth_1, system_parallella_base_0_0_synth_1, system_rv64_mmcm_0_0_synth_1... Run output will be captured here: system_RISCV_Rocket_Core_RV64_0_0_synth_1: /home/promach/Documents/Grive/Personal/Digital/Parallella/parallella-riscv/parallella/fpga/parallella_riscv/system.runs/system_RISCV_Rocket_Core_RV64_0_0_synth_1/runme.log system_auto_pc_3_synth_1: /home/promach/Documents/Grive/Personal/Digital/Parallella/parallella-riscv/parallella/fpga/parallella_riscv/system.runs/system_auto_pc_3_synth_1/runme.log system_auto_pc_2_synth_1: /home/promach/Documents/Grive/Personal/Digital/Parallella/parallella-riscv/parallella/fpga/parallella_riscv/system.runs/system_auto_pc_2_synth_1/runme.log system_auto_pc_1_synth_1: /home/promach/Documents/Grive/Personal/Digital/Parallella/parallella-riscv/parallella/fpga/parallella_riscv/system.runs/system_auto_pc_1_synth_1/runme.log system_auto_pc_0_synth_1: /home/promach/Documents/Grive/Personal/Digital/Parallella/parallella-riscv/parallella/fpga/parallella_riscv/system.runs/system_auto_pc_0_synth_1/runme.log system_sys_concat_intc_0_synth_1: /home/promach/Documents/Grive/Personal/Digital/Parallella/parallella-riscv/parallella/fpga/parallella_riscv/system.runs/system_sys_concat_intc_0_synth_1/runme.log system_processing_system7_0_0_synth_1: /home/promach/Documents/Grive/Personal/Digital/Parallella/parallella-riscv/parallella/fpga/parallella_riscv/system.runs/system_processing_system7_0_0_synth_1/runme.log system_rv64_sys_reset_0_0_synth_1: /home/promach/Documents/Grive/Personal/Digital/Parallella/parallella-riscv/parallella/fpga/parallella_riscv/system.runs/system_rv64_sys_reset_0_0_synth_1/runme.log system_proc_sys_reset_0_0_synth_1: /home/promach/Documents/Grive/Personal/Digital/Parallella/parallella-riscv/parallella/fpga/parallella_riscv/system.runs/system_proc_sys_reset_0_0_synth_1/runme.log system_parallella_base_0_0_synth_1: /home/promach/Documents/Grive/Personal/Digital/Parallella/parallella-riscv/parallella/fpga/parallella_riscv/system.runs/system_parallella_base_0_0_synth_1/runme.log system_rv64_mmcm_0_0_synth_1: /home/promach/Documents/Grive/Personal/Digital/Parallella/parallella-riscv/parallella/fpga/parallella_riscv/system.runs/system_rv64_mmcm_0_0_synth_1/runme.log [Thu May 25 14:14:43 2017] Launched synth_1... Run output will be captured here: /home/promach/Documents/Grive/Personal/Digital/Parallella/parallella-riscv/parallella/fpga/parallella_riscv/system.runs/synth_1/runme.log launch_runs: Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 1577.676 ; gain = 140.734 ; free physical = 152 ; free virtual = 5517 ## wait_on_run synth_1 [Thu May 25 14:14:43 2017] Waiting for synth_1 to finish... [Thu May 25 14:19:12 2017] synth_1 finished wait_on_run: Time (s): cpu = 00:04:23 ; elapsed = 00:04:29 . Memory (MB): peak = 1577.676 ; gain = 0.000 ; free physical = 643 ; free virtual = 5508 ## launch_runs impl_1 [Thu May 25 14:19:14 2017] Launched system_RISCV_Rocket_Core_RV64_0_0_synth_1, system_parallella_base_0_0_synth_1, system_rv64_mmcm_0_0_synth_1, synth_1... Run output will be captured here: system_RISCV_Rocket_Core_RV64_0_0_synth_1: /home/promach/Documents/Grive/Personal/Digital/Parallella/parallella-riscv/parallella/fpga/parallella_riscv/system.runs/system_RISCV_Rocket_Core_RV64_0_0_synth_1/runme.log system_parallella_base_0_0_synth_1: /home/promach/Documents/Grive/Personal/Digital/Parallella/parallella-riscv/parallella/fpga/parallella_riscv/system.runs/system_parallella_base_0_0_synth_1/runme.log system_rv64_mmcm_0_0_synth_1: /home/promach/Documents/Grive/Personal/Digital/Parallella/parallella-riscv/parallella/fpga/parallella_riscv/system.runs/system_rv64_mmcm_0_0_synth_1/runme.log synth_1: /home/promach/Documents/Grive/Personal/Digital/Parallella/parallella-riscv/parallella/fpga/parallella_riscv/system.runs/synth_1/runme.log [Thu May 25 14:19:14 2017] Launched impl_1... Run output will be captured here: /home/promach/Documents/Grive/Personal/Digital/Parallella/parallella-riscv/parallella/fpga/parallella_riscv/system.runs/impl_1/runme.log ## wait_on_run impl_1 [Thu May 25 14:19:14 2017] Waiting for impl_1 to finish... [Thu May 25 14:19:40 2017] impl_1 finished wait_on_run: Time (s): cpu = 00:00:25 ; elapsed = 00:00:26 . Memory (MB): peak = 1577.676 ; gain = 0.000 ; free physical = 619 ; free virtual = 5544 ## launch_runs impl_1 -to_step write_bitstream [Thu May 25 14:19:41 2017] Launched system_RISCV_Rocket_Core_RV64_0_0_synth_1, system_parallella_base_0_0_synth_1, system_rv64_mmcm_0_0_synth_1, synth_1... Run output will be captured here: system_RISCV_Rocket_Core_RV64_0_0_synth_1: /home/promach/Documents/Grive/Personal/Digital/Parallella/parallella-riscv/parallella/fpga/parallella_riscv/system.runs/system_RISCV_Rocket_Core_RV64_0_0_synth_1/runme.log system_parallella_base_0_0_synth_1: /home/promach/Documents/Grive/Personal/Digital/Parallella/parallella-riscv/parallella/fpga/parallella_riscv/system.runs/system_parallella_base_0_0_synth_1/runme.log system_rv64_mmcm_0_0_synth_1: /home/promach/Documents/Grive/Personal/Digital/Parallella/parallella-riscv/parallella/fpga/parallella_riscv/system.runs/system_rv64_mmcm_0_0_synth_1/runme.log synth_1: /home/promach/Documents/Grive/Personal/Digital/Parallella/parallella-riscv/parallella/fpga/parallella_riscv/system.runs/synth_1/runme.log [Thu May 25 14:19:41 2017] Launched impl_1... Run output will be captured here: /home/promach/Documents/Grive/Personal/Digital/Parallella/parallella-riscv/parallella/fpga/parallella_riscv/system.runs/impl_1/runme.log ## wait_on_run impl_1 [Thu May 25 14:19:41 2017] Waiting for impl_1 to finish... [Thu May 25 14:20:06 2017] impl_1 finished wait_on_run: Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 1577.676 ; gain = 0.000 ; free physical = 555 ; free virtual = 5551 cp: cannot stat './parallella_riscv/system.runs/impl_1/system_wrapper.bit': No such file or directory make: *** [../scripts/Makefrag:57: /home/promach/Documents/Grive/Personal/Digital/Parallella/parallella-riscv/parallella/fpga/parallella.bit] Error 1 # exit INFO: [Common 17-206] Exiting Vivado at Thu May 25 14:20:06 2017...